T2M GmbH IP Cores

Version 1.2 of the D-PHY specification is fully complied with by the MIPI D-PHY Analog RX IP Core.

• MIPI D-PHY

The D-PHY specification, version 1.2, is completely complied with by the MIPI D-PHY Analog TX IP Core.

• MIPI D-PHY

The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.

• Single-Protocol PHY
• In Production
• Immediate

The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• Single-Protocol PHY
• In Production
• Immediate

V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment c…

• V-By-One
• In Production
• Immediate

The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…

• TSMC
• 55nm
• GP
• In Production

The GPHY is a integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption.

• Single-Protocol PHY
• In Production
• Immediate

Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.

• SMIC
• 40nm
• LP
• In Production

A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data …

• USB 3.1

A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.

• USB 2.0

A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization.

• Multi-Protocol PHY
• In Production
• Immediate

1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…

• Single-Protocol PHY
• In Production
• Immediate

This GNSS RF Receiver IP is silicon-proven in TSMC40nm ULP process node, offers comprehensive support for all current satellite-b…

• GNSS
• In Production
• Immediate

This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to…

• Modulation Demodulation
• In Production
• Immediate
• Certified

The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…

• Channel Coding
• In Production
• Immediate
• yes

The BCH decoder has four main functional blocks along with memory blocks.

• Channel Coding
• In Production
• Immediate
• yes

The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling…

• Multi-Protocol PHY
• In Production
• Immediate

A physical layer IP for LVDS Receiver.

• Single-Protocol PHY
• In Production
• Immediate
• IEEE 1596.3 Standard

Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…

• Single-Protocol PHY
• In Production
• Immediate
• DisplayPort version 1.4 rec…

The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4.

• HDMI
• In Production
• Immediate
• HDMI 1.4 Receiver, HDCP rev…