Vendor: T2M GmbH Category: LPDDR

DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)

The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput.

Contact Provider Request Datasheet
Controller + PHY + 1 LPDDR5 TSMC 12nm FFC In Production View all specifications

Overview

The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL. The Combo PHY IP is also able to run on DDR4, DDR5, LPDDR5 modes separately.

Key features

  • Supported DRAM type: DDR5/DDR4/LPDDR5
  • Maximum controller clock frequency of 675MHz resulting in maximum DRAM data rate of 5400MT/s for DDR5
  • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 3200MT/s for DDR4
  • Maximum controller clock frequency of 600MHz resulting in maximum DRAM data rate of 4800MT/s for LPDDR5?
  • Interface: POD11/POD12/LVSTL05
  • Data path width scales in 8-bit increment
  • Four modules for flexible configuration: CA/DQ_X16/DQ_X8/ZQ
  • Programmable output impedance (DS)
  • Programmable on-die termination (ODT)
  • Core power:0.8V, Post-driver power (VDDQ):1.1V/1.2V/0.5V, Pre-driver power(VDDP): 1.1V/1.2V/1.05V
  • Receiver power (VDDI): 1.1V/1.2V/1.05V for DDR5/DDR4/LPDDR5
  • ESD: 2KV/HBM, 200V/MM, 500V/CDM
  • Support ZQ calibration
  • Support 4 ranks by each CA module
  • Support write-leveling, CBT
  • Support PHY internal VREFDQ auto decision
  • Per-bit deskew in read and write datapath

Block Diagram

DDR5/DDR4/LPDDR5 Combo PHY IP in 12FFC block diagram

What’s Included?

  • User Manual
  • Behaviour model, and protected RTL codes
  • Protected Post layout netlist
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC In Production

Specifications

Identity

Part Number
DDR5/DDR4/LPDDR5 Combo PHY IP in 12FFC
Vendor
T2M GmbH
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
LPDDR5

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

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Frequently asked questions about LPDDR Interface IP

What is DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)?

DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC) is a LPDDR IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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