MSquare IP Cores

Compatible with UCIe v1.1 specification; Features single-ended, source-synchronous, and DDR I/O signaling

• UCIe

Compatible with embedded display port v1.5/v1.4b specification; Four-lane main link with support for 8.1/5.4/4.32/3.24/2.7/2.43/2.16/1.62Gbps

• Single-Protocol PHY

Compliant with ONFI 5.1 specification; Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s; Supports matched or unmatched DQS

• Single-Protocol PHY

Compatible with JEDEC standards LPDDR4X , LPDDR5 and LPDDR5X SDRAMs; Supports for data transfer rate up to 8533Mbps

• Controller + PHY + 1
• LPDDR5X

Compatible with LPDDR4X, with a maximum rate up to 4267Mbps; Compliant with DFI 4.0 for PHY and control interfaces

• Controller + PHY + 1
• LPDDR4

The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.

• UCIe

Compliant with ONFI 5.0 specification; Supports NV-DDR2 mode; Supports NV-DDR3, NV-LPDDR4, and max rate up to 2400MT/s

• Single-Protocol PHY

Includes both PHY and Memory Controller components, supporting HBM3 SDRAM speeds ranging from 4.8Gbps/pin to 6.4Gbps/pin.

• Controller + PHY

Fully compliant with USB 3.2 Gen2x1 featuring PIPE 4.3 and USB 2.0 with a UTMI+ interface; Supports host, peripheral, and dual-role applications

• USB

Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications

• PCIe Gen4