Vendor: MSquare Category: Custom

C2C (Chip-to-Chip) interface IP

C2C&D2D Combo (UCIe-based) IP compliant with UCIe specification

Overview

The C2C (Chip-to-Chip) interface IP is a high-performance, low-latency, and power-efficient chip-to-chip interconnect solution designed for advanced multi-chiplet systems, AI accelerators, high-speed computing, and networking SoCs. It enables seamless, reliable data transmission between separate chips or heterogeneous dies through package interposer or PCB traces.

MSquare offers this silicon-proven IP with unique hybrid analog/digital architecture which has low power, compact area and robust performance. This UCIe&C2C combo IP contains Die-to-Die adapter layer and physical layer, each layer contains a sideband interface to provide a back-channel for link training and access of registers of the link partner.

Key features

  • C2C&D2D Combo (UCIe-based) IP compliant with UCIe specification
  • Standard Package with PCB, channel reach up to 100mm
  • 16-TX and 16-RX per-module, IO rate up to 32Gbps and independent full-duplex
  • Total solution with Controller+PHY
  • Supports AXI4/CXS.b interface (512-bit data width @1GHz Clock)

Specifications

Identity

Part Number
C2C
Vendor
MSquare
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

MSquare
HQ: China

Learn more about Custom IP core

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation.

Frequently asked questions about Custom Die-to-Die IP cores

What is C2C (Chip-to-Chip) interface IP?

C2C (Chip-to-Chip) interface IP is a Custom IP core from MSquare listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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