Vendor: MSquare Category: LPDDR

LPDDR6 PHY

Compatible with JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs

PHY LPDDR5 + 2 View all specifications

Overview

The LPDDR6 PHY IP is a high-speed, low-power physical layer interface IP designed for next-generation mobile memory, automotive applications, and high-bandwidth SoCs requiring power-efficient memory connectivity. It complies with the latest LPDDR6 standard and supports high-speed data transfer rates with advanced signal integrity and power management features.

MSquare' LPDDR6 IP is a transceiver IP between DRAM controller and DRAM device. Supporting DFI5.1 as a universal IP protocol. The maximum data rate of LPDDR6, LPDDR5X, LPDDR5 and LPDDR4X can reach 14400Mbps, 8533Mbps, 6400Mbps and 4266Mbps respectively with 16bit data width per channel. Figure 1 is LPDDR6 PHY block diagram in system application, which includes Data, Address transmit path, Receiver data path and PLL block, etc.

Key features

  • Compatible with JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
  • Support 10.667Gbps~14.400Gbps with BL=24/BL=48 and will be expanded to 16Gbps in the future
  • Support Dual sub channel architecture (2x12 bit), 32B minimal access granularity
  • Support Dynamic Efficiency Mode (DEM) + Static Efficiency Mode (SEM) for runtime power performance trade off
  • Support Dynamic NT-ODT
  • Support PHY Independence TX/RX Training mode
  • Support self-test mode with built-in bist
  • Support ZQ calibration, DFE mode
  • PLL & DLL included

Block Diagram

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Specifications

Identity

Part Number
LPDDR6
Vendor
MSquare
Type
Silicon IP
Controller / PHY
PHY

Standards & Interfaces

Memory
LPDDR5 , LPDDR5X , LPDDR6

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

MSquare
HQ: China

Learn more about LPDDR IP core

Practical AI Silicon on Mainstream Node using LPDDR

This solution brief highlights how Samsung’s mainstream 8nm process node and LPDDR5X (LP5X) memory together deliver an optimized balance of performance, bandwidth, power efficiency, and cost. The combination enables scalable AI inference across diverse computing environments, from edge devices and AI appliances to emerging inference-focused AI infrastructure, making advanced AI deployment more accessible for startups, fabless innovators, and OEMs alike.

LPDDR flash: A memory optimized for automotive systems

Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle.

Hardware Acceleration of Block-Diffusion LLM for Edge Devices

The authors co-design WIFiV-LPDDR, a wide-I/O LPDDR system for precision-tagged reads, BRQ-KV for a canonical low-rank-plus-INT8-residual prefix with query-dependent per-entry precision, and DAT-FFN for drift-mapped canonical replacement, adjacent-stage-corrected low-bit delta, or cached-state carry while keeping live activations unquantized.

Frequently asked questions about LPDDR Interface IP

What is LPDDR6 PHY?

LPDDR6 PHY is a LPDDR IP core from MSquare listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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