Vendor: MSquare Category: UCIe

D2D UCIe 1.0

The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.

Overview

The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package. MSquare's M2LINK D2D Solution, which is compatible with the UCIe v1.0 specification, includes both a Die-to-Die adapter layer and a physical layer. Each layer features a sideband interface that provides a back-channel for link training and register access of the link partner, as shown in Figure 1. This Unique hybrid analog/digital architecture offers low power consumption, compact footprint, and robust performance, making it highly suitable for applications in high-performance computing, AI, multimedia SoCs, and Die-to-Die interconnections.

 

Key features

  • Compatible with UCIe v1.0 specification
  • Single-ended, source synchronous and DDR IO Signaling
  • Supports 32 bits(16bits TX + 16bits RX) data bus per module for standard package
  • High clock frequency, up to 8GHz
  • 16 Gbps/lane data rate
  • 512Gbps (256Gbps TX + 256Gbps RX) bandwidth per module for standard package
  • High energy efficiency with ~0.8pJ/bit for standard package
  • Built in Test and diagnostics (Functional(PRBS), scan, at speed external loopback)
  • The advanced process of 12nm

Block Diagram

Specifications

Identity

Part Number
D2D UCIe 1.0
Vendor
MSquare
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: China

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Frequently asked questions about UCIe IP cores

What is D2D UCIe 1.0?

D2D UCIe 1.0 is a UCIe IP core from MSquare listed on Semi IP Hub.

How should engineers evaluate this UCIe?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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