Vendor: Synopsys, Inc. Category: PCI Express

PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)

The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Expre…

PCIe 7.0 View all specifications

Overview

The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Express 7.0 specification, and can be configured by the user to support Endpoint (EP), Root Port, Dual Mode (DM), or Switch Port (SW) applications. The low-latency controller with MultiStream architecture allows a full 128GT/s x16 lane bandwidth with support for up to 1024-bit data paths, while enabling timing closure at 1GHz and 2GHz. The controller can ensure optimal flow with multiple sources and in multi-virtual channel implementations. Support for host, device, and dual mode enables early interoperability in absence of available 7.0 hosts and interop partners. Designers can achieve maximum throughput for Arm-based SoCs with the controller’s support for the Arm AXI and for advanced host features including deferrable memory writes. The controller's reliability, availability and serviceability (RAS) features enhance data integrity, simplify firmware development and improve link bring-up.
The Synopsys Controller IP for PCIe 7.0 seamlessly interoperates with the silicon-proven PHY IP for PCIe 7.0 in advanced FinFET processes to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 128GT/s PCIe 7.0 technology. To protect against data tampering and physical attacks in high performance computing SoCs using the PCIe 7.0 interface, Synopsys offers standards-compliant IDE Security IP Modules, including TDISP and Host TEE (Arm CCA) support.

Key features

  • Supports all required features of the PCI Express 7.0, 6.x, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
  • Full Transaction Layer, Data Link Layer and Physical Layer
  • Supports up to sixteen 128.0, 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
  • Available in 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
  • 125 MHz, 250 MHz, 500 MHz, 1 GHz and 2 GHz operation
  • Supports PIPE 6.x and PIPE 7.x interface including variable clock and variable data widths up to 128-bit
  • Application interfaces include the Synopsys native interface or the optional single- or dual-port 512-bit/1024-bit AXI Bridge supporting Arm AMBA 5/4/3 AXI
  • Optional embedded HyperDMA controller with up to 64 read and 64 write channels plus descriptor pre-fetch for high throughput with minimal SoC resource overhead
  • Configurable and efficient retry buffer design for low latency and area
  • Supports automatic lane reversal and polarity inversion
  • Supports the full range of PCIe-defined maximum packet sizes (128B to 4KB) and read request sizes (128B to 4KB)
  • Performs PCI Express flow-control credit management, configurable for infinite credits for any traffic type
  • Supports legacy INTx, MSI, and MSI-X interrupt semantics
  • Configurable filtering rules for posted, non-posted and completion traffic
  • Configurable BAR (up to 6) filtering, IO filtering, configuration filtering and completion lookup/timeout
  • Support for multiple application clients
  • In-band and out-of-band access to configuration space registers and external user application registers with local bus controller
  • Expansion ROM, VPD, and Device Serial Number support
  • Broad support for optional ECNs, including the latest features, like Unordered IO

Benefits

  • Supports all required features of the PCI Express 7.0 (64 128 GT/s) specification
  • Allows a full 128GT/s x16 lane bandwidth with up to 1024-bit data path implementations
  • Supports advanced RAS data protection features including ECC
  • Advanced RAS-DES features for simplified bring-up and debug
  • Supports the Synopsys native interface or the optional Arm® AMBA® 5/4/3 AXI application interface
  • Configurable for low power, small area and low latency
  • Enables efficient embedded DMA applications with Synopsys HyperDMA™
  • Standards-compliant Integrity and Data Encryption (IDE) Security Module protects data transfers over PCIe 7.0 interfaces
  • TDISP support for PCIe for SR-IOV and hardware security via IDE

What’s Included?

  • The coreConsultant utility to guide designers through the installation configuration, verification, and implementation of the IP; Verilog RTL code; Example PHY interfaces; ASIC and FPGA synthesis scripts; Verification environment; Synopsys Verification IP for PCI Express; Documentation: release notes, installation/integration guide, application notes, user manual

Specifications

Identity

Part Number
dwc_pci_express_gen7_controller
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

PCIe Version
PCIe 7.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

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Frequently asked questions about PCIe IP cores

What is PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)?

PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications) is a PCI Express IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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