Vendor: Synopsys, Inc. Category: Single-Protocol PHY

USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation

The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…

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GlobalFoundries 22nm FDX View all specifications

Overview

The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers (Device, Host, or Dual-Role Device) with HDCP 2.2 content protection, verification IP, IP subsystems, IP prototyping kits and IP software development kits (SDKs). These elements accelerate development of advanced chip designs delivering video, data and power over a single Type-C connector.

The USB-C 3.1/DisplayPort Tx 1.3 Tx IP is targeted for integration into SoCs that support connections to high-definition (HD), 2K, 4K, and 8K Ultra High Definition (UHD) display from mobile devices, set-top boxes and other applications requiring fast data transfer and output of high-resolution content. The IP solution delivers up to 10 Gbps data rates and simplifies users’ USB connection with reversible plug orientation and cable direction, bi-directional power and the DisplayPort alternate mode. The DisplayPort 1.3 alternate mode uses existing SuperSpeed USB lanes over USB Type-C connectors and cables to deliver up to 32.4 Gbps maximum link bandwidth with each of the four lanes running at 8.1 Gbps. The IP USB-C 3.1/DisplayPort 1.3 Tx IP solution simplifies integration and reduces system-level costs by removing requirements for external crossbar switch components for the USB and DisplayPort datapaths.

The USB-C 3.1/DisplayPort 1.3 Tx IP solution integrates HDCP 2.2 content security, which is required to play back UHD 4K and higher-resolution content over DisplayPort 1.3 alternate mode. It creates a secure connection between a source and display by using industry standard public key and advanced encryption algorithms for successful content transfer. Synopsys’ HDCP 2.2 content protection IP provides designers with a complete and highly secure implementation of the HDCP 2.2 standard, including the entire control plane processing with authentication and key exchange protocols, as well as key stream generation. Incorporating HDCP 2.2 content protection in the USB-C 3.1/DisplayPort 1.3 Tx IP solution helps designers meet the stringent compliance requirements of the DCP LLC licensing authority.

As the leading supplier of USB IP, Synopsys enables designers to accelerate the integration of high-performance USB Type-C connectivity into their SoCs, while enabling secure delivery of high-definition video content.

Key features

  • Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.3 Tx PHYs, USB-C 3.1/DisplayPort 1.3 Tx controllers with HDCP 2.2 and HDCP 1.4 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
  • Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.3 Tx supporting RBR, HBR1, HBR2 and HBR3 bitrates
  • Controllers support Device, Host, and Dual-Role Device USB-C 3.1 as well as DisplayPort 1.3 Tx with HDCP 2.2 content protection
  • DesignWare USB-C 3.1/DisplayPort 1.3 Tx PHY optimized for USB Type-C connectivity, conforming to latest USB 3.1 and DisplayPort 1.3 specifications
  • Supports Type-C Port Controller, Type-C Port Controller Interface and Type-C Port Manager specifications for flexible hardware and software partitioning

Block Diagram

dwc_usbc31dptxphy_gf22fdsoins block diagram

Benefits

  • USB-C 3.1/DisplayPort 1.3 Tx Controller IP
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
    • DisplayPort 1.3a Transmit features optimized for USB Type-C
    • Integrates with DesignWare HDCP 2.2 Embedded Security Modules
  • USB-C 3.1/DisplayPort 1.3 Tx PHY IP
    • Supports 10 Gbps and 5 Gbps data rates
    • Supports RBR, HBR1, HBR2 and HBR3 data rates
    • Low active and standby power
    • Small area for low silicon cost
    • Optimized USB Type-C connectivity support

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX —

Specifications

Identity

Part Number
dwc_usbc31dptxphy_gf22fdsoins
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about Single-Protocol PHY IP core

Accelerating the Development of TLM-2.0 Models Using Model Authoring Kits (MAKs)

Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.

Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems

Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

Frequently asked questions about Single-Protocol PHY IP

What is USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation?

USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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