MIPI I3C Controller IP core

The MIPI I3C Controller IP is a highly optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and FPGA technologies. The Chip Interfaces  MIPI I3C IP  is used to connect multiple Targets to one or more Controllers with Secondary controllers having the capability to take ownership of the bus. The IP can act as the Bus Controller or Secondary Controller with the inclusion of the Target Engine, it is also possible to set up as a simple Target or Composite Device with multiple Virtual Targets. The MIPI I3C IP from Chip Interfaces supports SDR and HDR transmission modes over a single or multiple lanes allowing it to reach transfer speeds of up to 100 Mbps. The Chip Interfaces MIPI I3C Controller IP is backward compatible with MIPI I3C versions 1.1 and 1.0, as well as with I2C. The Application data interface follows the TCRI v1.0 specification.

The Chip Interfaces MIPI I3C Controller IP core has been heavily tested in System Verilog random regression environment.

Controller Role

The MIPI I3C Controller IP core is a highly optimized Silicon Agnostic implementation of the MIPI I3C protocol version 1.1.1 and MIPI TCRI v1.0. It is used to connect I3C and I2C target devices over a shared 2-wire bus, targeting both ASIC and FPGAs. It delivers all features of the standard and allows for the ability to configure included features.

The IP supports Multiple Controllers on the bus with proper Controller handoff procedures to Secondary Controllers as well as I2C and I3C target devices making it possible to build the most complex of systems.

• Delivering Performance
  •  Fully compliant with MIPI I3C v1.1.1 Specification
  •  TCRI v1.0 Compliant
  •  Supports Bus with Multiple Controllers
  •  Supports Hot Join mechanism
  •  Supports all I3C CCC common command codes
  •  Supports SDR, HDR-DDR, HDR-TSP/TSL, HDR-BT
  •  Supports Multi Lane operation (all formats)
  •  Supports Async Modes 0-3
  •  Supports Target Reset
  •  Supports Device to Device tunneling (D2DT)
  •  Supports Early Termination
  •  Supported Roles:
    •      Controller
    •     Secondary Controller
    •  Target
    •  Composite device with Virtual Targets
• Easy to use
  • Solid documentation including an integration guide
  • Easy to use RTL test environment
  • No special software is required
  • Strong engineering support for bring-up
• Robust
  • UVM based Verification
  • Lint/CDC checked
• Silicon Agnostic
  • Targeting both ASICs and FPGAs

• Test Environment: MIPI I3C IP is tested in a UVM based regression environment for full functional coverage
• Silicon Agnostic: Designed in Verilog and targeting both ASICs and FPGAs
• Active Support: All support is actively provided by engineers directly

• The IP Core can be delivered in Source code or Encrypted format.
• The following deliverables will be provided with the IP Core license:
  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, and Test Script.
  • Basic RTL Test Bench
  • Synthesis Scripts
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Test Report, Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request