Vendor: Missing Link Electronics Category: Ethernet

TCP/UDP/IP Network Protocol Accelerator Platform

Accelerate Network Protocols with FPGA TCP/UDP/IP Stack The German Fraunhofer Heinrich-Hertz-Institute (HHI) has partnered with M…

Overview

Accelerate Network Protocols with FPGA TCP/UDP/IP Stack

The German Fraunhofer Heinrich-Hertz-Institute (HHI) has partnered with MLE to market the proven network accelerators “TCP/IP & UDP Network Protocol Accelerator Platform (NPAP)”.  This customizable solution enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G / 2.5G / 5G / 10G / 25G / 40G / 50G / 100G Ethernet links.

MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer’s ASIC or FPGA project settings, world-wide.

Key features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
  • 128-bit wide bi-directional data paths with streaming interfaces
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • DPDK Stream interface (optional)
  • Corundum NIC integration with performance DMA and PCIe (optional)

Block Diagram

Benefits

  • Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”)
  • Increase network throughput and reduce transport latency
  • Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”)
  • Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI
  • All MAC / Ethernet / IPv4 / UDP / TCP processing is implemented in HDL code, synthesizable to modern FPGAs and ASIC
  • User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs

Applications

  • FPGA-based SmartNICs
  • In-Network Compute Acceleration (INCA)
  • Hardware-only implementation of TCP/IP in FPGA
  • PCIe Long Range Extension
  • Networked storage, such as iSCSI
  • Test & Measurement connectivity
  • Automotive backbone connectivity based on open standards
  • Video-over-IP for 3G / 6G / 12G transports
  • Increase throughput for 10G/25G/50G/100G Ethernet
  • Reduce latency in System-of-Systems communication

Specifications

Identity

Part Number
NPAP
Vendor
Missing Link Electronics
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Ethernet IP core

Enhancing Ethernet Security with MACsec

Ethernet was originally designed for high-speed data transfer and interoperability between devices. However, traditional Ethernet does not provide built-in mechanisms for securing data traffic, such as encryption or authenticity protection. This is where MACsec comes into the picture.

What Makes Ethernet IP Truly Automotive-Grade

This blog examines what separates truly automotive-grade Ethernet IP from generic implementations across functional safety, time-sensitive networking, security, observability, lifecycle management, and the integration disciplines that only become visible once a program is deep into development.

Frequently asked questions about Ethernet IP cores

What is TCP/UDP/IP Network Protocol Accelerator Platform?

TCP/UDP/IP Network Protocol Accelerator Platform is a Ethernet IP core from Missing Link Electronics listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP