Vendor: HCL Technologies Category: I2C / I3C

I2C Controller

I2C Dual mode IP ( master and slave mode) with APB interface to support the standard I2C Bus Protocol and APB5 Interface on the A…

Overview

I2C Dual mode IP ( master and slave mode) with APB interface to support the standard I2C Bus Protocol and APB5 Interface on the Application side. It is an Inter Integration Circuit IP that provides a simple way to talk between integrated circuits by using 4 wires: two SCL (Serial Clock) lines and two SDA (Serial Data) lines. These lines are divided into input and output lines. This IP acts as a transmitter as well as a receiver.

Key features

  •  Configuration: Controller and Target
    •  Programmable via Host interface
    •  Only one configuration will be active at a given time
  •  Different bus modes:
    • a. Standard Mode (0 to 100 kbit/s)
    • b. Fast Mode (<= 400 kbit/s)
    • c. Fast Mode Plus (<= 1000 kbit/s)
    • d. High Speed Mode (<= 3.4 Mbit/s)
  •  Target Addressing: 7bit
  •  Level or Edge Interrupt defined via parameter
  •  Standard APB5 Interface used for Host interface
  •  Separate clock domain for IP Core functionality and Host Interface.
    • a. Parameter used to select same clock or different clocks for IP Core functionality and Host Interface.
  •  Buffers on both Transmit and Receive path with parameterizable depths.
  •  DMA interface for Host to DMA data into/from the IP Buffers.

Block Diagram

Benefits

  •  Dual mode IP (master and slave mode).
  •  Supports different modes of transfer .
  •  Supports DMA interface also .
  • Separate clock domain for IP Core functionality and Host Interface.
  •  I2C can communicate with 128 different slaves since it supports 7 bit addressing mode (2 ^7 = 128).

What’s Included?

  •  Design IP
  •  integration manual
  •  Design Constraints
  •  Lint CDC Waivers

Specifications

Identity

Part Number
HCLT_I2C DUAL MODE IP
Vendor
HCL Technologies
Type
Silicon IP

Provider

Learn more about I2C / I3C IP core

Casting a wide safety net through post processing Checking

In this paper, we explain how we adopted the post processing method to make sure we check for signatures that are expected are present in the log files. This acted as a safety net when engineers made inadvertent mistakes and introduced issues in the code base.

Low Power Design in SoC Using Arm IP

This paper discusses about the low power IP components from ARM can help one to realize the low power features in the SoC. It should be noted that this paper does not discuss about the low power concepts or design techniques. Rather, it focuses on the implementation approaches using ARM low power IP.

Frequently asked questions about I2C / I3C IP cores

What is I2C Controller?

I2C Controller is a I2C / I3C IP core from HCL Technologies listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP