PCIe 6.0 / CXL 3.0 PHY & Controller

The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications. These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications.

The PCIe 6.x/CXL 3.0 PHY is a highly configurable IP supporting data rates of up to 64Gbps per lane. It features NRZ signaling for 2.5, 5.0, 8.0, 16.0, and 32GT/s, as well as PAM4 signaling for 64GT/s. The PHY seamlessly interoperates with Innosilicon’s PCIe 6.x and CXL 3.0 controllers, ensuring robust performance and compatibility.

The Gen6 PCI Express Controller supports both Root Complex (RC) and Endpoint (EP) applications. It is a high-performance, high-reliability solution with low latency, minimal area, and power efficiency. The controller supports up to x8 lanes across all generations, fully compliant with the PCI Express Base Specification, Revision 6.0.

The CXL 3.0 Controller supports three key protocols, enabling seamless integration with accelerators and memory devices. Sharing the PCIe6.0/5.0 electrical layer, this controller is fully compliant with the Compute Express Link Specification, Revision 3.1, ensuring optimal performance for advanced compute and memory expansion applications.
 

• Configurable host or device operation
• Configurable CXL.cache and/or CXL.mem protocol support
• Configurable high speed AXI-S style streaming parallel user interfaces for maximum throughput
• CXL transaction layer implements endpoint address decoding for simple/efficient support of DRAM channels with two configurable levels of decoding to support intra-endpoint and inter-endpoint interleaving schemes
• Configurable for IDE support for CXL.cache/CXL.mem in all operating modes
• 64B/128B Datapath at 1GHz

• Includes required features in the PCIe Specification 6.0 and CXL Specification Revision 3.1
• High utilization FLIT packing with round-robin access between protocols and fairness between channels in a protocol
• Low latency
• Supports CXL 2.0 68B FLIT, and CXL 3.0 256B FLIT and CXL 3.0 256B latency optimized FLIT operating modes

• CXL Controller Functional Specification
  • Hardware architecture
  • Interface descriptions
  • Module descriptions
  • Register descriptions
  • Clocking and reset strategy
  • Configuration guide
• RTL source code written in Verilog for all modules excluding the IDE modules
• Encrypted RTL for all IDE-related modules
• Synthesis and timing constraints and user documentation
• IP system sanity test bench and user documentation