Vendor: Xilinx, Inc. Category: PCI Express

Endpoint for Gen1 PCI Express

Virtex-5 FPGA, Gen1 PCI Express The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-la…

Overview

Virtex-5 FPGA, Gen1 PCI Express

The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-lane complete endpoint core and a PCI Express PIPE Interface Protocol Layer core. In addition a PCI Express Endpoint Development Kit is also available. These solutions can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions help customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces.

Key features

  • Protocol and electrically compatible
  • Complete endpoint solution includes physical, link and transaction, and configuration management modules
  • Both 8-lane and 4-lane configurations auto negotiate down to a 1-lane configuration
  • Supports packet-oriented LocalLink Interface
  • Synchronous point-to-point communication
  • Upstream and downstream flow control
  • Fully compliant with PCI Express transaction ordering rules
  • Efficient link bandwidth utilization
  • Error detection and recovery
  • Supports maximum payload of 512 bytes
  • Design verified by a Xilinx proprietary testbench
  • Tested at PCI-SIG compliance workshop and included on PCI Express Integrators List
  • PCI Express Xilinx Development Kit available from NitAl

Specifications

Identity

Part Number
EF-DI-PCIEXP-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about PCI Express IP core

How to design FPGA-based advanced PCI Express endpoint solutions

Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, enterprise, mobile, workstation, networking, communica

Repeatable results with design preservation

Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well. The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations.

Frequently asked questions about PCIe IP cores

What is Endpoint for Gen1 PCI Express?

Endpoint for Gen1 PCI Express is a PCI Express IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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