Vendor: Xilinx, Inc. Category: Ethernet

XPS Ethernet Lite

Included in EDK at no additional charge The Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable…

Overview

Included in EDK at no additional charge

The Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification.

The Ethernet Lite MAC supports the IEEE Std. 802.3 Media Independent Interface (MII) to industry standard Physical Layer (PHY) devices and communicates to a processor via a Processor Local Bus (PLB) interface. The design provides a 10 Megabits per second (Mbps) and 100 Mbps (also known as Fast Ethernet) Interface. The goal is to provide the minimal functions necessary to provide an Ethernet interface with the least resources used.

Key features

  • PLB interface is based on PLB v4.6 specification
  • Memory mapped direct I/O interface to the transmit and receive data dual port memory
  • Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
  • Independent internal 2K byte Tx and Rx dual port memory for holding data for one packet
  • Optional dual buffer memories, 4K byte ping-pong, for Tx and Rx

Specifications

Identity

Part Number
XPS Ethernet Lite
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Ethernet IP core

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Frequently asked questions about Ethernet IP cores

What is XPS Ethernet Lite?

XPS Ethernet Lite is a Ethernet IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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