Vendor: Xilinx, Inc. Category: CAN / CAN-FD / CAN-XL

XPS CAN

Included with CAN IP Solutions.

Overview

Included with CAN IP Solutions.

The Controller Area Network (CAN) LogiCORE™ IP product provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6. This PLB slave interface supports single beat read and write data transfers (no burst transfers).

Key features

  • Conforms to the ISO 11898 -1, CAN 2.0A, and CAN 2.0B standards
  • Supports Industrial (I) and Extended Temperature Range (Q) grade device support
  • Supports both standard (11-bit identifier) and extended (29-bit identifier) frames
  • Supports bit rates up to 1 Mbps
  • Transmit message FIFO with a user-configurable depth of up to 64 messages
  • Transmit prioritization through one High-Priority Transmit buffer
  • Automatic re-transmission on errors or arbitration loss
  • Receive message FIFO with a user- configurable depth of up to 64 messages
  • Acceptance filtering (through a user-configurable number) of up to 4 acceptance filters
  • Sleep Mode with automatic wakeup
  • Loop Back Mode for diagnostic applications
  • Maskable Error and Status Interrupts
  • Readable Error Counters

Specifications

Identity

Part Number
EF-DI-CAN-XA-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about CAN / CAN FD / CAN XL IP cores

What is XPS CAN?

XPS CAN is a CAN / CAN-FD / CAN-XL IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this CAN / CAN-FD / CAN-XL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CAN / CAN-FD / CAN-XL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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