Vendor: Xilinx, Inc. Category: I2C / I3C

XPS IIC Bus Interface

Included in EDK at no additional charge starting in EDK9.2i This product specification defines the architecture, hardware (signal…

Overview

Included in EDK at no additional charge starting in EDK9.2i

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.

Key features

  • Master or slave operation
  • Multi-master operation
  • Software selectable acknowledge bit
  • Arbitration lost interrupt with automatic mode switching from master to slave.
  • Calling address identification interrupt with automatic mode switching from master to slave
  • START and STOP signal generation/detection
  • Repeated START signal generation
  • Acknowledge bit generation/detection
  • Bus busy detection
  • Fast mode 400 KHz operation or standard mode 100 KHz
  • 7 bit or 10 bit addressing
  • General call enable or disable
  • Transmit and receive FIFOs - 16 bytes deep
  • Throttling
  • General purpose output, 1 bit to 8 bits wide
  • Dynamic Start/Stop generation

Specifications

Identity

Part Number
XPS IIC Bus Interface
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about I2C / I3C IP core

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Frequently asked questions about I2C / I3C IP cores

What is XPS IIC Bus Interface?

XPS IIC Bus Interface is a I2C / I3C IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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