Configurable SPDIF-AES3 Receiver
The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds …
- SPDIF
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Configurable SPDIF-AES3 Receiver
The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds …
SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interfa…
Asynchronous Communications Interface Adapter (ACIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking custo…
Tri-Speed Ethernet MAC Core IP
The Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits…
Aliathon’s VT/TU Mapper performs the insertion and extraction of PDH signals into or from multiple VT/TU paths.
syn1588® enabled IEEE 1588 compliant clock synchronisation
The syn1588® Clock_M IP core offers the full syn1588® technology with a suitable number of trigger and IO events supported.
Polybus offers a family of InfiniBand Link Layer Cores ranging from a Single Data Rate 4X core (10GBit/Second) to a Quad Data Rat…
The PLBv46 to PCI Full Bridge design provides full bridge functionality between the Xilinx PLB and a 32-bit Revision 2.2 complian…
XPS_LL_TEMAC Ethernet core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 …
USB 1.1 Device, Software Based Enumeration (USB11SR)
The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface.
32-bit Initiator/Target for PCI Single Project Spartan Series
32-bit Initiator/Target for PCI™ Single Project Spartan® family enables designers to build a customized 32-bit system running at …
32-bit Initiator/Target for PCI
32-bit Initiator/Target for PCI™ enables designers to build a customized 32-bit system running at speeds up to 66 MHz that perfor…
32-bit & 64-bit Initiator/Target for PCI Product Bundle
DO-DI-PCI-AL rolls both the 32-bit and 64-bit Initiator/Target for PCI™ LogiCORE™ IP cores together into one convenient bundle.
The OPB to PCI 32/33 Bridge is offered as an evaluation core in the EDK.
Embedded Tri-mode Ethernet MAC Wrapper
The CORE Generator™ Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper file…
The EP423 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode.
A Free parameterizable core that can be used with Gigabit Ethernet MAC, soft and Embedded Tri-Mode Ethernet MAC Cores.
USB Function Controller, Fully Compatible with USB 2.0
USB core is the VHDL model of USB Function Controller, which is fully compatible with the USB 2.0 specification.
Aliathon’s SONET/SDH Framer Core implements Transport Overhead framing functions for SONET/SDH links, including frame generation …