AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
SPI / QSPI XSPI
XPS Serial Peripheral Interface
The XPS Serial Peripheral Interface (SPI) connects to the PLB (Processor Local Bus) and provides a serial interface to SPI device…
Overview
The XPS Serial Peripheral Interface (SPI) connects to the PLB (Processor Local Bus) and provides a serial interface to SPI devices such as SPI EEPROMs. The SPI protocol, as described in the Motorola M68HC11 data sheet, provides a simple method for a master and a selected slave to exchange data.
Key features
- Connects as a 32-bit slave on PLB V4.6 buses of 32,
- Supports four signal interface (MOSI, MISO, SCK and SS)
- Supports slave select (SS) bit for each slave on the SPI bus
- Supports full-duplex operation
- Supports master and slave SPI modes
- Supports programable clock phase and polarity
- Optional transmit and receive FIFOs
- Optional transmit and receive FIFOs scanning of a peripheral
- Supports back-to-back transactions
- Supports automatic or manual slave select modes
- Supports local loopback capability for testing
Specifications
Identity
Part Number
XPS Serial Peripheral Interface
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is XPS Serial Peripheral Interface?
XPS Serial Peripheral Interface is a SPI / QSPI XSPI IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.