Overview
The SVRPlus supports a clock lane and 4 data lanes,
each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
The highly parallel architecture of the SVRPlus2500 allows
relatively slow internal clocks of approximately 160Mhz.
The SVRPlus2500 supports all CSI2 mandatory and optional video formats,
including compressed video formats. Noise resiliency is improved using Pseudo-Random-Binary
Sequence (PRBS) encoding on the data lanes.
The SVRPlus2500 complies with MIPI CSI2 and DPHY specifications (version 2.0 of both documents).
The SVRPlus2500 receives a single clock lane and four data lanes, complying with MIPI DPHY 2.0,
at up to 2.5Gbps per lane. The DPHY input data is converted to parallel lanes by FPGA-specific
high-speed 1:16 DESERS. The data comprises CSI2 2.0 short, long and calibration packets.
The SVRPlus2500 decodes and outputs the received pixels, at 4,8 or 16 parallel pixels.
Line error information can be read from on-IP registers, inducing BER measurements
Learn more about MIPI PHY IP core
The imbalance between I/O speed and internal logic speed in integrated circuits has shifted in recent years in favor of the I/O. While in the past, the performance of integrated circuits was often limited by the I/O rate, today, in both ASICs and FPGAs, internal logic struggles to keep up with the I/O performance.
In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
VLSI Plus today announced the availability of the CSI2-MUX-A1-F – a MIPI® CSI2 transceiver, connecting to up to 4 CSI2 camera inputs, and outputting a multiplexed CSI2 stream with 4 data lanes, at up to 1.5Gbps per lane.
VLSI Plus today announced at the MWC conference the availability of the SVT-CS4-AP2 – a MIPI® CSI2 compliant serial video transmitter, supporting multiple concurrent video sources, and employing from 1 to 4 DPHY lanes at up to 1.5Gbps per lane.
VLSI Plus today announced the availability of Alias-DT option, which enables outputting multiple pixels per clock, in all its MIPI® CSI2 Receiver IP cores (the SVR family).
VLSI Plus today announced the availability of the SVRPlus-CSI2-F a 64 bit serial video receiver, supporting MIPI® CSI2 and extensions to CSI2 with up to 8 data lanes and two clock lanes, and outputting 1, 2 or 4 pixels per clock.
