Vendor: VLSI Plus Ltd Category: MIPI PHY

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver

The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.

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Overview

The SVRPlus supports a clock lane and 4 data lanes,
each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
The highly parallel architecture of the SVRPlus2500 allows
relatively slow internal clocks of approximately 160Mhz.
The SVRPlus2500 supports all CSI2 mandatory and optional video formats,
including compressed video formats. Noise resiliency is improved using Pseudo-Random-Binary
Sequence (PRBS) encoding on the data lanes.

The SVRPlus2500 complies with MIPI CSI2 and DPHY specifications (version 2.0 of both documents).

The SVRPlus2500 receives a single clock lane and four data lanes, complying with MIPI DPHY 2.0,
at up to 2.5Gbps per lane. The DPHY input data is converted to parallel lanes by FPGA-specific
high-speed 1:16 DESERS. The data comprises CSI2 2.0 short, long and calibration packets.
The SVRPlus2500 decodes and outputs the received pixels, at 4,8 or 16 parallel pixels.
Line error information can be read from on-IP registers, inducing BER measurements

Key features

  • One clock lane and four data lanes.
  • Up to 2.5Gbps per lane.
  • Support of all CSI2 primary and secondary data formats.
  • 128-bit internal data buses, for high throughput.
  • 4, 8 or 16 pixel outputs per clock.
  • Full data-compression support, including Predictor-1 and Predictor-2.
  • VCX (extended virtual channel) support – up to 16 channels.
  • PRBS scrambling per lane.
  • Calibration sequence detection for inter-lane de-skewing.
  • 16-bit serial to parallel converter (off-IP).

Block Diagram

SVRPlus2500 block diagram

Benefits

  • CSI2 rev 2.0
  • DPHY rev 2.0
  • Low clock rating for easy timing closure
  • PRBS support
  • 4/8/16 – pixel output per clock
  • calibration support
  • 16 virtual channels

Specifications

Identity

Part Number
SVRPlus2500
Vendor
VLSI Plus Ltd
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

VLSI Plus Ltd
HQ: Israel
Contact VLSI Plus Ltd

Learn more about MIPI PHY IP core

High Bit-Rate Controllers for MIPI CSI2

The imbalance between I/O speed and internal logic speed in integrated circuits has shifted in recent years in favor of the I/O. While in the past, the performance of integrated circuits was often limited by the I/O rate, today, in both ASICs and FPGAs, internal logic struggles to keep up with the I/O performance.

Frequently asked questions about MIPI PHY IP

What is 2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver?

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver is a MIPI PHY IP core from VLSI Plus Ltd listed on Semi IP Hub.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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