Overview
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of the SVTPlus2500 allows relatively slow internal clocks of approximately 160Mhz. The SVTPlus supports all CSI2 mandatory and optional video formats, including compressed video formats. Noise resiliency is improved using Pseudo-Random-BinarySequence (PRBS) encoding on the data lanes.
The SVTPlus2500 complies with MIPI CSI2 and DPHY specifications (version 2.0 of both documents).
The SVTPlus2500 receives parallel pixels from a video source (1,2,4 or 8 pixels per clock). The pixels are translated to MIPI CSI2 packets and output from the SVTPlus2500 by high-speed parallel and low-power signals. The high-speed parallel signals are converted by an FPGA-specific high-speed 16:1 seriallizer, to DPHY high-speed signals, at up to 2.5Gbps per lane. An external LVDS to DPHY device converts the high speed and the low-power inputs to DPHY signals, transmitted over a single clock lane and up to four data lanes. A simple CPU is typically required for configuration and, if needed, for diagnostics.
Learn more about MIPI IP core
The imbalance between I/O speed and internal logic speed in integrated circuits has shifted in recent years in favor of the I/O. While in the past, the performance of integrated circuits was often limited by the I/O rate, today, in both ASICs and FPGAs, internal logic struggles to keep up with the I/O performance.
In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
A two data-lane Serial Video Receiver (SVR), compatible with both MIPI CSI2 and SMIA CCP2 standards, with speeds of up to 2Gbps, is presented.
With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.
Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.
High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.
