Vendor: VLSI Plus Ltd Category: MIPI

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter

The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.

Overview

The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of the SVTPlus2500 allows relatively slow internal clocks of approximately 160Mhz. The SVTPlus supports all CSI2 mandatory and optional video formats, including compressed video formats. Noise resiliency is improved using Pseudo-Random-BinarySequence (PRBS) encoding on the data lanes.

The SVTPlus2500 complies with MIPI CSI2 and DPHY specifications (version 2.0 of both documents).

The SVTPlus2500 receives parallel pixels from a video source (1,2,4 or 8 pixels per clock). The pixels are translated to MIPI CSI2 packets and output from the SVTPlus2500 by high-speed parallel and low-power signals. The high-speed parallel signals are converted by an FPGA-specific high-speed 16:1 seriallizer, to DPHY high-speed signals, at up to 2.5Gbps per lane. An external LVDS to DPHY device converts the high speed and the low-power inputs to DPHY signals, transmitted over a single clock lane and up to four data lanes. A simple CPU is typically required for configuration and, if needed, for diagnostics.

Key features

  • Configurable 1 to 4 data lanes.
  • Up to 2.5Gbps per lane.
  • Support of all CSI2 primary and secondary data formats.
  • 128-bit internal data buses, for high throughput.
  • Selectable 1-, 2-, 4- or 8-pixel input per clock (1,2 or 4 for pixels with more than 16 bits per pixel).
  • Full data-compression support, including Predictor-1 and Predictor-2.
  • VCX (extended virtual channel) support – up to 16 channels.
  • PRBS scrambling per lane.
  • Calibration sequences for inter-lane de-skewing.
  • 16-bit parallel to serial converter (off-IP).
  • Configurable timing control for all DPHY parameters.
  • Excel sheets for easy timing-parameter optimization.

Block Diagram

SVTPlus2500 block diagram

Benefits

  • CSI2 rev 2.0
  • DPHY rev 2.0
  • Low clock rating for easy timing closure
  • PRBS support
  • 8/16 – pixel input per clock
  • calibration support
  • Programmable timing parameters
  • 16 virtual channels

Specifications

Identity

Part Number
SVTPlus2500
Vendor
VLSI Plus Ltd
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

VLSI Plus Ltd
HQ: Israel

Learn more about MIPI IP core

High Bit-Rate Controllers for MIPI CSI2

The imbalance between I/O speed and internal logic speed in integrated circuits has shifted in recent years in favor of the I/O. While in the past, the performance of integrated circuits was often limited by the I/O rate, today, in both ASICs and FPGAs, internal logic struggles to keep up with the I/O performance.

Generating High Speed CSI2 Video by an FPGA

In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.

Frequently asked questions about MIPI IP cores

What is 2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter?

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter is a MIPI IP core from VLSI Plus Ltd listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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