Vendor:
Blue Cheetah Analog Design, Inc.
Category:
Custom
Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.
Overview
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP. The PHY is compatible with UCIe and BoW specifications. It is intended to interface with a second interface that complies with the same requirements. Multiple PHY slices can be stacked for higher bandwidth per millimeter of silicon die edge. UCIe compatible D2D solutions support UCIe v1.1 FLIT Data Interface (FDI). BlueLynx enables customers to configure the bump pitch to accommodate advanced packaging. The bump pitch will determine the overall PHY hard macro area.
Key features
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
- Support for bonded and independent slices
- Side band and redundancy support
- Staggered bump pitch for organic substrate (example macro above)
- Bump pitch customizable from 45um (advanced) to 180um (standard) package applications
- Each slice (TX+RX) macro area set by macro bump pitch (multiple slices can be stacked)
- Support for N/S and E/W Poly Orientations
- Programmable alignment between link layer and PHY clocks to aid timing closure
- APB pclk pass-through to the link layer clock domain for reset of synchronous flops
- Integrated, background-calibrated DLL with duty-cycle correction for input clock
- Firmware-controlled startup and shutdown through control and status registers
- JTAG and/or APB register access
- Built in self-test (BIST) and diagnostic logic
- On Demand eye plotter
- Integrated microcontroller, PLL
Benefits
- Customizable
- BlueLynx PHY and link layer architecture is customizable to support a wide range of physical and complex system bandwidth use cases.
- Configurable
- Whether your application is cost-sensitive or performance-intensive, BlueLynx offers versatile packaging options, including standard and advanced, with support for multiple bump pitches, metal stacks, and poly orientations.
- Optimized
- BlueLynx D2D IP solutions offer power-optimized performance from 8 Gb/s to 16, 24, 32, and beyond.
- Multiple Processes
- BlueLynx IP is available at 16nm,12nm, 7nm, 6nm, 5nm, 4nm, 3nm, and below across multiple semiconductor foundries and supports various medal stacks.
- Silicon Proven
- Customers receive industry-standard ASIC integration views with reference collateral, including board package designs and a bring-up platform and software required for first-pass silicon success in the shortest time.
Specifications
Identity
Part Number
BlueLynx PHY IP
Vendor
Blue Cheetah Analog Design, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Custom IP core
Would custom memory ease your SoC design?
A case study shows how custom memory design can adapt to functional, timing, or layout requirements of a particular SoC.
Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation.
Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform
As AI workloads scale exponentially, bandwidth has become the new bottleneck. This article explores how Celestial AI’s Photonic Fabric™ redefines interconnect performance, and how Sofics’ low-cap ESD and power clamp IP enabled its integration on TSMC’s 5nm platform.
A New Era for Edge AI: Codasip’s Custom Vector Processor Drives the SYCLOPS Mission
See how Codasip Studio enables SYCLOPS to implement a customizable RISC-V Vector processor, accelerating the future of open-source, high-performance AI compute at the Edge.
RISC-V basics: The truth about custom extensions
The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), edge computing, automotive, and industrial markets continue to expand, they are driving a fundamental shift in processor design.
Frequently asked questions about Custom Die-to-Die IP cores
What is Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications?
Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications is a Custom IP core from Blue Cheetah Analog Design, Inc. listed on Semi IP Hub.
How should engineers evaluate this Custom?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.