Vendor: Blue Cheetah Analog Design, Inc. Category: Custom

Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications

BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.

Overview

BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP. The PHY is compatible with UCIe and BoW specifications. It is intended to interface with a second interface that complies with the same requirements. Multiple PHY slices can be stacked for higher bandwidth per millimeter of silicon die edge. UCIe compatible D2D solutions support UCIe v1.1 FLIT Data Interface (FDI). BlueLynx enables customers to configure the bump pitch to accommodate advanced packaging. The bump pitch will determine the overall PHY hard macro area.

Key features

  • High data rate of 2–24 Gb/s
  • Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
  • Very low latency of < 2 ns PHY-to-PHY
  • Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
  • Support for bonded and independent slices
  • Side band and redundancy support
  • Staggered bump pitch for organic substrate (example macro above)
  • Bump pitch customizable from 45um (advanced) to 180um (standard) package applications
  • Each slice (TX+RX) macro area set by macro bump pitch (multiple slices can be stacked)
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  • Support for N/S and E/W Poly Orientations
  • Programmable alignment between link layer and PHY clocks to aid timing closure
  • APB pclk pass-through to the link layer clock domain for reset of synchronous flops
  • Integrated, background-calibrated DLL with duty-cycle correction for input clock
  • Firmware-controlled startup and shutdown through control and status registers
  • JTAG and/or APB register access
  • Built in self-test (BIST) and diagnostic logic
  • On Demand eye plotter
  • Integrated microcontroller, PLL

Benefits

  • Customizable
    • BlueLynx PHY and link layer architecture is customizable to support a wide range of physical and complex system bandwidth use cases.
  • Configurable
    • Whether your application is cost-sensitive or performance-intensive, BlueLynx offers versatile packaging options, including standard and advanced, with support for multiple bump pitches, metal stacks, and poly orientations.
  • Optimized
    • BlueLynx D2D IP solutions offer power-optimized performance from 8 Gb/s to 16, 24, 32, and beyond.
  • Multiple Processes
    • BlueLynx IP is available at 16nm,12nm, 7nm, 6nm, 5nm, 4nm, 3nm, and below across multiple semiconductor foundries and supports various medal stacks.
  • Silicon Proven
    • Customers receive industry-standard ASIC integration views with reference collateral, including board package designs and a bring-up platform and software required for first-pass silicon success in the shortest time.

 

Specifications

Identity

Part Number
BlueLynx PHY IP
Vendor
Blue Cheetah Analog Design, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about Custom Die-to-Die IP cores

What is Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications?

Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications is a Custom IP core from Blue Cheetah Analog Design, Inc. listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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