Vendor: Faraday Technology Category: Multi-Protocol PHY

16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+

Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provid…

UMC 28nm HPC View all specifications

Overview

Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provide optimization of power, performance and area to meet the growing needs for high bandwidth and low latency in the applications of consumer, access layer networking device to core/enterprise layer.

The silicon verified 16Gbps SerDes PHY supports the optimization of SoC chip designs to enable the infrastructure of 10G/40G Ethernet, PCIe 4.0, 5G, and most xPON applications. Compared with the other latest Serdes solutions, it is the only solution that supports both PCIe 4.0 and 10G xPON ONU/OLT in 28nm node.

This full-duplex, high-performance and many-protocols compatible SerDes solution comes with a scalable PMA which can be applied to a wide range of applications across copper and backplane channels with total insertion loss more than 30dB. It is also compatible with standard PCS and controller, and provides flexible design environment for users to customize PCS and controller integration.

Key features

  • Support PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
  • Support xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym/Asym 10GEPON
  • Support IEEE 802.3 1G to 40G backplane (KX, KX4/XAUI, KR & KR4), port side (XFI, SFF-8431/SFI and CR4)
  • Support JESD204B/C for high-speed ADC/DAC and FPGA interface
  • Support SGMII and QSGMII (1.25 to 5G)
  • Support CEI-6G and CEI-11G
  • Support Serial Rapid IO (SRIO)
  • Support CPRI
  • Multi-Interface to enable 3rd party’s PCS/MAC’s direct connection to PMA
  • Soft PCS IP available for PCIe 4.0 and bifurcation applications
  • PMA data width for 16/20/32/40 bits
  • Full-duplex lane configuration of x1, x2, x4
  • Ultra-low-power 3 TAP FIR voltage-mode driver with programmable swing and amplitude
  • Receiver with adaptive CTLE/VGA equalizer, and 5 TAP DFE
  • Multiple internal/external loopbacks (TX to RX, RX to TX, RX loopback after S2P with RX clock)
  • On-chip eye scan monitor for testing
  • Built-in power-saving states
  • Built-in PRBS & programmable pattern generator and checker
  • FOM for link training
  • Extensive auto-calibration and BIST engine for performance tuning and self-diagnostics
  • Support up to 600 ppm offset and up to 5000ppm SSC

Block Diagram

16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+ block diagram

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC —

Specifications

Identity

Part Number
16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Vendor
Faraday Technology
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Faraday Technology
HQ: Taiwan

Learn more about Multi-Protocol PHY IP core

System-on-chip (SoC) design is all about IP management

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual property (IP) blocks from multiple vendors. This makes managing silicon IP the dominant task in the design process.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+?

16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+ is a Multi-Protocol PHY IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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