USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.
- USB 2.0
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.
Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core
NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State…
MIPI I3C Slave v1.1 Controller IP enables efficient data flow for sensor integration.
As Sensor data rate increases, there is a necessity to have control information flowing to and from sensors at an efficient data …
I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products, compliant with …
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications
10Gbps Multi-Link and Multi-Protocol PHY IP
Designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express (PCIe) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, QSGMII
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
The combination PHY is SATA (Serial ATA) compliant with SATA 3.0 Specification, PCIe (Peripheral Component Interconnect Express) …
OSU processor, optimized for E1/FE/GE services with Ethernet over SDH over OTU0/OTU1 lines
The TPS3215MP OSU processor is an IP Core solution designed for Xilinx FPGAs.
JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 40LL
The JESD204B Tx-Rx PHY IP interface, which offers total support for the JESD204B synchronous and serial data interface, is aligne…
ARINC 429 IP-Core with DO-254 Package
The ARINC-429 IP Core is a multi-channel ARINC 429 transmitter and receiver core for serial communication in airborne application…
028TSMC_LVDS_01 is a library including: Transmitter LVDS driver (TX_LVDS); Receiver LVDS driver (RX_LVDS); Reduced range link rec…
SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Intercon…
PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification.
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL
The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interf…
JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 28HPC
The JESD204B.01 version specification is compatible with the JESD204B Tx-Rx PHY IP interface, which offers support for the JESD20…
JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 14SF++
In addition providing support for the JESD204B synchronous serial interface, the JESD204B Tx-Rx PHY IP interface is consistent wi…
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP
Full support for the JESD204B synchronous serial interface, compliant with the JESD204B.01 version specification, is provided via…