Vendor: T2M GmbH Category: I2C / I3C

MIPI I3C Master v1.1 Controller IP offers impressive data transmission capacity for sensor integration.

I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products, compliant with …

Overview

I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products, compliant with MIPI Alliance. Our I3C supports several communication formats all sharing a two wire interface - SDA and SCL. SDA is a bidirectional data pin while SCL can be either a clock pin or a data pin while in HDR mode. The type of communication supported by I3C. I2C-like communication with SCL clock speed up to 12.5 MHz , MIPI-defined transmissions that allow the master to communicate to one or all slaves on the bus.

HDR mode using ternary number symbols to achieve two data transmissions per equivalent clock cycle. A subset of I2C communication to legacy I2C slaves, if present on the bus. Slave initiated request to master, e.g. In-band interrupt, address request.

Key features

  • Compliant with the MIPI Alliance Draft Specification for I3C Version 0.5 Revision 1.0
  • Supports all modes of Master – SDR [12.5 MHz], HDR and HDR-DDR, I2C Modes.
  • Supports interrupt handling.
  • Enables peer to peer communication.
  • Detects hot Join of slave devices.
  • Dynamic Addressing support.
  • Support In-Band Interrupt
  • Automatic retry configurability for failure slave transactions.
  • Error check and reporting of master and slave errors.
  • Highly configurable and gate efficient core.
  • Compliant with AMBA 3 APB Protocol Specification v1.0 for register access.
  • Easy integration and co-existence with I3C devices.
  • Supports Legacy I2C mode
  • Can be configured to work as secondary master
  • Dynamic addressing assignment capability
  • Support for slave generated in-band interrupts
  • Memory for retaining bus device addresses

Block Diagram

MIPI I3C Master v1.1 Controller IP block diagram

Benefits

  • I3C Master can be configured to work as the secondary master
  • I3C Slave configuration – HDR-DDR Slave, SDR-only Slave
  • System Access: APB or AXI
  • Configurable FIFOs

Applications

  • Mobile
  • IOT
  • Automotive
  • In Environmental sensing and other applications like NFC, etc.
  • Mechanical/Motion related application like to name a few: Compass/Magnetometer/Gyro/Accelerometer/Proximity/Touchscreen/ Grip/Time of Flight/Audi/ultrasonic, etc.
  • In biometrics/Health application like to name few: Fingerprint/glucometer/Heart-Rate, etc.

What’s Included?

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Specifications

Identity

Part Number
MIPI I3C Master v1.1 Controller IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Frequently asked questions about I2C / I3C IP cores

What is MIPI I3C Master v1.1 Controller IP offers impressive data transmission capacity for sensor integration.?

MIPI I3C Master v1.1 Controller IP offers impressive data transmission capacity for sensor integration. is a I2C / I3C IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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