The Universal Media Access Controller (UMAC) ensures efficient data flow, low latency, and optimized power usage.
- Ethernet
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Universal Media Access Controller (UMAC) ensures efficient data flow, low latency, and optimized power usage.
UCIe Die-to-Die Chiplet Controller
The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.
32G PHY in TSMC (N5A, N3A) for Automotive
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across back…
32Gbps Pseudo Random Bit Sequence Generator/Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps.
UHF RFID EPC Gen2V2 physical interface
180SMIC_G2PHY_01 is an IP intended for use in passive UHF transponder applications.
Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems
Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…
UHF RFID EPC Gen2 physical interface
130GF _G2PHY_02 is the IP intended for use in passive UHF transponder applications.
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits.
Pulse Per Second (PPS) Clock to PPS core
NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configura…
The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a …
The Synopsys 800G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the 400G IEEE 802.3bs standard, provides a set of fe…
Synopsys’ CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 32GT/s and suppo…
Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…