Vendor: Innosilicon Technology Ltd Category: Single-Protocol PHY

USB3.2 PHY & Controller

USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications.

Overview

USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications. Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals. In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers.

The USB 3.2 PHY is a highly programmable module that converts high-speed serial data into parallel data, compliant with the PIPE standard. The PHY supports USB 3.2 Gen 2x2, delivering SuperSpeed data rates of up to 20Gbps. Streamlined production testing is enabled through built-in self-test (BIST), multiple loopback modes, and boundary scan. Its modular and flexible design ensures compatibility with the latest USB Type-C configurations, integrating all necessary I/Os and ESD protection in a single drop-in block. Like all Innosilicon IPs, our USB 3.2 solution is fully customizable, enabling seamless integration and optimization for your specific application requirements.

Key features

  • Supports 20Gb/s serial data transmission rate
  • Utilizes a 16-bit or 32-bit interface to transmit and receive USB SuperSpeed data
  • Allows integration of high speed components into a single functional block.
  • Data and clock recovery from serial stream on the USB Enhanced SuperSpeed bus
  • Holding registers to stage transmit and receive data
  • Supports direct disparity control for use in transmitting compliance pattern
  • 8b/10b, 128/132b encode/decode and error indication
  • Receiver detection
  • Low Frequency Periodic Signaling (LFPS) Transmission
  • Built in self-test and loopback test
  • Selectable Tx Margining, FFE and signal swing values
  • Selectable Rx CTLE peaking range and DFE taps
  • Auto calibrated and tunable on die termination (ODT)
  • Integrated IO with ESD protection aimed at HBM 2KV and CDM 250V
  • Well-tuned T-coil to promote ultra-high bandwidth

Block Diagram

Benefits

  • Small die size
  • Low pin counts
  • Low power consumption
  • Fully customizable

Applications

  • Enterprise Computing
  • Storage Networks
  • Network-on-Chip (NoC)
  • Automotive
  • Server Connectivity
  • GPU Interfacing

What’s Included?

  • Verilog Sim Behavioral simulation model for the PHY
  • Encrypted IO spice netlist for SI evaluation
  • Integration Guidelines
  • Test Guidelines
  • GDSII Layout and layer map for foundry merge
  • Place and Route LIB and LEF views for the AFE
  • LVS and DRC verification reports

Specifications

Identity

Part Number
USB3.2 PHY & Controller
Vendor
Innosilicon Technology Ltd
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.2

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

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In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

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Frequently asked questions about Single-Protocol PHY IP

What is USB3.2 PHY & Controller?

USB3.2 PHY & Controller is a Single-Protocol PHY IP core from Innosilicon Technology Ltd listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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