Overview
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets the requirements, both for SMBSDA and SMBSCK acceptable timing intervals.
The DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
DPSMBUS supports transmission speeds up to 3.4 Mb/s, which cover all three acceptable speeds for SMBus and PMBus:
100 kHz,
400 kHz,
1 MHz.
The DPSMBUS in the slave mode has attached internal FIFO, which can store even up to 256 bytes. It is also possible to read the status of the transmission including a step where communication failed. Except for SMBSDA and SMBSCK, there is also SMBAlert, which is defined as an interrupt signal between master and slave devices. Due to the SMBAlert handler, DPSMBUS supports arbitration of slave devices.
The DPSMBUS in PMBus version accepts ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses. Also, it is possible to perform group command protocol and even extended command functionality. There are included CONTROL and WRITE PROTECT signals along with their functionality for device supervision.
Learn more about I2C / I3C IP core
The I2C (Inter-Integrated Circuit) Bus invented in 1980 by Philips Semiconductors (NXP Semiconductors today) was a massive step forward in simplifying communications in embedded systems. It is a simple two-wire interface for synchronous, multi-master/multi-slave, single ended serial communication. Fast forward 45 years to today and it is still widely used for attaching low speed peripheral Integrated Circuits (ICs), processors and microcontrollers. But silicon today has changed...
Early in my career selling chips for Motorola Semiconductor, the ability to spin derivative microcontroller chips for a customer’s specific requirement was relatively straightforward. If the volume looked reasonable, we would tape-out a new chip with a few added features because mask costs and wafers were relatively inexpensive at the larger process nodes. The customer won by getting an MCU tailored to their specific need, and Motorola won by gaining a more committed customer plus another SKU that could be sold to other customers – boosting ROI. With the migration to higher cost FinFET nodes, those times are long gone as the economics no longer work.
Sharmion Kerley, MIPI Director of Marketing and Membership
Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.
