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DESPI eSPI Controller IP Core and DESPI eSPI IP Core Target deliver a complete, high-speed eSPI interface solution for FPGA and ASIC designs.
Vendor:
Digital Core Design
Category:
I2C / I3C
SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
Overview
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets the requirements, both for SMBSDA and SMBSCK acceptable timing intervals.
The DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
DPSMBUS supports transmission speeds up to 3.4 Mb/s, which cover all three acceptable speeds for SMBus and PMBus:
100 kHz,
400 kHz,
1 MHz.
The DPSMBUS in the slave mode has attached internal FIFO, which can store even up to 256 bytes. It is also possible to read the status of the transmission including a step where communication failed. Except for SMBSDA and SMBSCK, there is also SMBAlert, which is defined as an interrupt signal between master and slave devices. Due to the SMBAlert handler, DPSMBUS supports arbitration of slave devices.
The DPSMBUS in PMBus version accepts ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses. Also, it is possible to perform group command protocol and even extended command functionality. There are included CONTROL and WRITE PROTECT signals along with their functionality for device supervision.
It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets the requirements, both for SMBSDA and SMBSCK acceptable timing intervals.
The DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
DPSMBUS supports transmission speeds up to 3.4 Mb/s, which cover all three acceptable speeds for SMBus and PMBus:
100 kHz,
400 kHz,
1 MHz.
The DPSMBUS in the slave mode has attached internal FIFO, which can store even up to 256 bytes. It is also possible to read the status of the transmission including a step where communication failed. Except for SMBSDA and SMBSCK, there is also SMBAlert, which is defined as an interrupt signal between master and slave devices. Due to the SMBAlert handler, DPSMBUS supports arbitration of slave devices.
The DPSMBUS in PMBus version accepts ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses. Also, it is possible to perform group command protocol and even extended command functionality. There are included CONTROL and WRITE PROTECT signals along with their functionality for device supervision.
Key features
- Master operation: Master transmitter, Master receiver
- Slave operation: Slave transmitter, Slave receiver
- Supports up to 3.4 Mb/s, which covers all acceptable speeds for SMBus and PMBus
- Performs arbitration and clock synchronization
- Multi-master system supported
- Interrupt generation along with SMBAlert bus signal
- Meets the requirements for SMBSDA and SMBCLK acceptable timing intervals
- Allows operation from a wide range of input clock frequencies (built-in 8-bit timer)
- The simple interface allows easy connection to microcontrollers
- User-defined timings
- DSPMBus driver supports all SMBus and PMBus communication sequences
- Fully synthesizable
- Static synchronous design with positive edge clocking and configurable reset
- DSPMBUS driver has implemented CRC8 calculation required for PEC bytes
- SMBUS
- Compatible with ALERT RESPONSE ADDRESS, and DEVICE DEFAULT ADDRESS predefined addresses
- Implemented FIFO, which can store up to 256 bytes
- Supports SMBAlert arbitration
- PMBUS
- Has implemented CONTROL and WRITE PROTECT signals required for PMBus protocol
- Compatible with ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses
- Accepts group command protocol and extended command functionality
- Implemented FIFO, which can store up to 256 bytes
Benefits
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
- Full customization
- Global sales network
- Technology independence
- Professional service
- Getting a sillicon proven IP
Applications
- Serial Data communications applications
- Modem interface
- Embedded microprocessor boards
What’s Included?
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Specifications
Identity
Part Number
DPSMBUS
Vendor
Digital Core Design
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Poland
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Frequently asked questions about I2C / I3C IP cores
What is SMBUS & PMBUS Master/Slave controller?
SMBUS & PMBUS Master/Slave controller is a I2C / I3C IP core from Digital Core Design listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.