Overview
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB Highspeed and Full speed), and USB 3.0 compliant with USB 3.0. Due to the provision of extra PLL control, reference clock control, and integrated power gating control, lower power consumption is obtained.
Additionally, because the aforementioned low power mode option is customizable, the PHY is extensively useful for a variety of situations with diverse power consumption considerations.
Learn more about Multi-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
