Overview
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification. The Gen 3 has a capability for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Furthermore, because the low power mode option is customizable, the PHY is extensively relevant for a variety of situations with varying power consumption considerations.
T2M provides the best-in-class, highly configurable PCIe 3.0 PHY that complies with ECN 1.0a and PCie 3.0 specifications and is aimed at both client and corporate applications. The eight-lane arrangement of the PHY IP allows for maximum throughput while supporting a wide range of applications. It can be tailored by the client for lower data rates (Gen2) or fewer lanes. Additionally, it offers L1 substates L1.1 and L1.2, allowing for easy integration in applications with strict power requirements while maintaining minimal silicon area.
Learn more about Multi-Protocol PHY IP core
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
Steven Brown
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
