Overview
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification. The Gen 3 has a capability for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Furthermore, because the low power mode option is customizable, the PHY is extensively relevant for a variety of situations with varying power consumption considerations.
T2M provides the best-in-class, highly configurable PCIe 3.0 PHY that complies with ECN 1.0a and PCie 3.0 specifications and is aimed at both client and corporate applications. The eight-lane arrangement of the PHY IP allows for maximum throughput while supporting a wide range of applications. It can be tailored by the client for lower data rates (Gen2) or fewer lanes. Additionally, it offers L1 substates L1.1 and L1.2, allowing for easy integration in applications with strict power requirements while maintaining minimal silicon area.
Learn more about Multi-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
