PHY and SerDes IP cores are essential building blocks for high-speed data transmission in modern semiconductor designs. This category includes physical layer IP and serializer/deserializer solutions used to implement reliable chip-to-chip, die-to-die, backplane and interface connectivity across networking, compute, storage, automotive and consumer applications.
Browse PHY / SerDes semiconductor IP for high-speed interfaces requiring robust signal integrity, scalable lane configurations, low power and standards-oriented interoperability. Compare controller-adjacent PHY IP, generic SerDes architectures and specialized high-speed connectivity solutions from multiple vendors for integration into ASICs, SoCs and advanced package designs.
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization.
The MIPI C-PHY IPis a high-frequency, low-power, low cost, physical layer.
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver
The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
Silicon Proven 1G Ethernet PHY IP as Whitebox
1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…
MIPI D-PHY Transmitter/Receiver for TSMC 22nm ULL
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 22nm ULL process.
MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI
The MIPI® D-PHY Transmitter/Receiver is useful 4 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of Samsung 28nm FD-SOI process.
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 40nm LP process.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 supporting…
16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provid…
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.
The T40LP_MIPIDPHYV01 IP is a MIPI D-PHY and LVDS based on TSMC 40nm LP process.
The IP is a USB PHY based on TSMC 180nm process.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Networking SerDes IP, Silicon Proven in ST 28FDSOI
The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling…
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with P…