Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP
The Display Port 1.4 Rx IP Channel's maximum capacity is supported.
- UMC
- 40nm
- LP
- In Production
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP
The Display Port 1.4 Rx IP Channel's maximum capacity is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
PCIe is the most common protocol in high speed serial standards to connect components in embedded systems.
USB 3.0 PHY IP, Silicon Proven in UMC 28HPC
For peripheral devices, there is a Universal Serial Bus (USB) transceiver available.
USB 2.0 PHY IP, Silicon Proven in UMC 28HPC
The USB 2.0 PHY IP Core offers a physical layer (PHY) solution for high performance and low power.
USB 2.0 PHY IP, Silicon Proven in UMC 40LP
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for excellent performance and low power consumption.
USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
With this PHY IP, it supports both USB 3.1 Gen1 and Gen2.
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
It supports both USB 3.1 Gen1 and Gen2 with this PHY IP.
USB 3.0 PHY IP, Silicon Proven in SMIC 14SF+
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.0 PHY IP, Silicon Proven in UMC 40SP
A Universal Serial Bus (USB) transceiver is available for peripheral devices.
USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
The USB 2.0 PHY IP Core is a solution for the physical layer (PHY) that prioritizes both high performance and low power consumpti…
USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumpti…
USB 2.0 PHY IP, Silicon Proven in SMIC 14SF+
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumpti…
USB 2.0 PHY IP, Silicon Proven in UMC 55SP/EF
The USB2.0 PHY IP is a physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…
USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
A Universal Serial Bus (USB) transceiver which is provided for peripheral devices.