Vendor: T2M GmbH Category: Single-Protocol PHY

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP

Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).

UMC 40nm LP In Production View all specifications

Overview

Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2). programmable analogue features, a built-in equaliser, 100-ohm termination resistors, common-mode biassing of the CDR bandwidth, the regulator voltage, the BGR voltage, and the terminator resistance Support 1.8V/0.9V power supplies for PLL testing and internal analogue signal monitoring.

Key features

  • eDP version 1.4a / DP version 1.4 compliant transmitter
  • Supports HDCP1.4 and HDCP2.2(Optional)
  • Supports Forward Error Correction (Optional)
  • Consists of configurable (4/2/1) link channels and one AUX channel
  • Supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate (ie 2.16Gbps etc)
  • Supports main link operation with 1 or 2 or 4 lanes
  • Supports both Default and Enhanced Framing Mode
  • Supports SST mode
  • Supports video packet and audio packet (8ch max)
  • Supports both Normal and Alternate Scrambler Seed Reset
  • Supports E-EDID data reading via I2C-over-AUX transaction
  • Supports Video test pattern generator (compliant with DP link CTS v1.2)
  • Configuration registers programmable via AMBA interface
  • Silicon Proven in UMC 40nm SP

Block Diagram

DisplayPort 1.4 Tx PHY IP in 40SP block diagram

What’s Included?

  • Verilog RTL or netlist source code of LINK controller.
  • Abstracted timing models for synthesis and STA
  • Timing constrains for synthesis and physical layout
  • Behavioural Verilog Model, simulation test bench, run control scripts, and test stimuli
  • Physical design database
  • Integration guidelines
  • Reference software sample code

Silicon Options

Foundry Node Process Maturity
UMC 40nm LP In Production

Specifications

Identity

Part Number
DisplayPort 1.4 Tx PHY IP in 40SP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP?

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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