Vendor: T2M GmbH Category: Single-Protocol PHY

USB 3.0 PHY IP, Silicon Proven in UMC 28HPC

For peripheral devices, there is a Universal Serial Bus (USB) transceiver available.

USB 3.0 UMC 28nm HPC In Production View all specifications

Overview

For peripheral devices, there is a Universal Serial Bus (USB) transceiver available. The USB 3.0 (USB SuperSpeed), USB 2.0 PIPE, and UTMI standards are all met by the PHY. The USB3.0 PHY IP transceiver is designed to consume little power and take up little space on the chip, without compromising speed or data throughput. A complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalisation circuit are all included in the USB3.0 PHY IP to assure full support for high-performance designs. Multiple IP sources are supported for the USB3 MAC layer through the standard PHY interface (PIPE). Internal test control and permissible parameter tweaking for analogue circuits with integrated Jitter Injection Output and Built-in Self-Test Jitter minimization by the use of consistent power.

Key features

  • Compliant with Universal Serial Bus 3.0 Specification
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Compliant with PIPE 3.0
  • Compliant with Universal Serial Bus 2.0 Specification
  • High-speed data transfer rate: 480 Mbps
  • Compliant with legacy USB 1.1
  • Full-speed data transfer rate: 12 Mbps
  • Compliant with UTMI 1.05 Specification
  • Operating Voltage: 1.1V and 3.3V
  • Support low jitter automatically calibrated oscillator for crystal-less mode
  • Support 125/250 MHz with 32/16-bit mode for USB 3.0
  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing
  • Silicon Proven in UMC 28HPC.

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behavior model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
USB 3.0 PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is USB 3.0 PHY IP, Silicon Proven in UMC 28HPC?

USB 3.0 PHY IP, Silicon Proven in UMC 28HPC is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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