Vendor: T2M GmbH Category: Single-Protocol PHY

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP

This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…

TSMC 40nm LP In Production View all specifications

Overview

This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth, Equalizer Strength, Terminator Resistor, and BGR Voltage, up to 5.4 Gbps per channel (HBR2). It also includes testability options such as PLL alone test and analog signal monitor, ensuring comprehensive functionality for signal processing and testing in digital display systems.

Key features

  • DisplayPort version 1.4 compliant receiver
  • PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate
  • Integrated 100-ohm termination resistors with common-mode biasing
  • Integrated equalizer with tunable strength
  • eDP version 1.4a / DP version 1.3 compliant
  • receiver Supports HDCP1.4 and HDCP2.2(Optional)
  • Consists of configurable (4/2/1) link channels and one AUX channel
  • Supports 1.62Gbps (RBR), 5.4Gbps (HBR2) and 8.1 Gbps (HBR3) bit rate
  • Supports main link operation with 1 or 2 or 4 lanes
  • Supports both Default and Enhanced Framing Mode Supports SST mode
  • Supports video packet and audio packet
  • Supports 18 / 24-bit RGB digital video output format Master I2C interface for DDC connection
  • Interface to external HDCP key storage
  • Configuration registers programmable via AMBA interface
  • Configurable analog characteristics
  • CDR bandwidth
  • Equalizer strength
  • Terminator resistance
  • BGR voltage
  • Regulator voltage
  • Support PLL test and internal analog signal monitor
  • 1.8V/0.9V power supply
  • Silicon Proven in TSMC 40nm LP.

Block Diagram

DisplayPort v1.4 Rx PHY IP in 40LP block diagram

What’s Included?

  • Verilog RTL or netlist source code of LINK controller.
  • Abstracted timing models for synthesis and STA
  • Timing constrains for synthesis and physical layout
  • Behavioral Verilog Model, simulation test bench, run control scripts, and test stimuli
  • Physical design database
  • Integration guidelines
  • Reference software sample code

Silicon Options

Foundry Node Process Maturity
TSMC 40nm LP In Production

Specifications

Identity

Part Number
DisplayPort v1.4 Rx PHY IP in 40LP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP?

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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