Vendor: Terminus Circuits Pvt Ltd. Category: Single-Protocol PHY

PCI Express PHY

PCIe is the most common protocol in high speed serial standards to connect components in embedded systems.

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TSMC 12nm FFC View all specifications

Overview

PCIe is the most common protocol in high speed serial standards to connect components in embedded systems. It leverages SerDes (Serializer/De-serializer) technology to deliver throughput and latency performance greater than what is possible with wide parallel bus technology.

The vendor offers best-in-class PHY IP for PCIe 4.0/3.0/2.0. The PHY is designed for low latency, low power, small form factor, high interface speeds for high performance computing. The PHYs comes complete with a physical media attachment (PMA) hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) and soft macro for PCIe that is PIPE4.3 compliant.

Key features

  • Quad PCIe 16/8/5/2.5 Gbps per lane
  • Tight control over termination resistor (~50 Ohm) with on chip calibration
  • Tight skew control of 1UI between lanes of the PMA
  • 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
  • Lowest latency
  • Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
  • Programmable/automatic calibration of key circuits (pre-emphasis, eye-diagram monitoring / DFE tap calibration / offset calibration)
  • CDR logic for better data alignment and locking
  • Support for bifurcation and quadfurcation modes
  • 3-tap Rx DFE (decision feedback equalizer)
  • Programmable internal/external loopback modes between TX and RX
  • SRnS (Separate Reference no Spread) support
  • Includes ESD structures
  • Operation across a wide temperature range (-40 C to +125 C)

What’s Included?

  • User and integration guides
  • Netlist
  • Timing library
  • Register map
  • Verilog
  • IBIS-AMI models
  • LEF views
  • Layout Versus Schematic (LVS)
  • Design Rule Check (DRC) reports
  • Silicon

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC —

Specifications

Identity

Part Number
PCI Express PHY
Vendor
Terminus Circuits Pvt Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Terminus Circuits Pvt Ltd.
HQ: Bangalore- 560094, India
Contact Terminus Circuits Pvt Ltd.

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Frequently asked questions about Single-Protocol PHY IP

What is PCI Express PHY?

PCI Express PHY is a Single-Protocol PHY IP core from Terminus Circuits Pvt Ltd. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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