Vendor: T2M GmbH Category: Single-Protocol PHY

USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC

It supports both USB 3.1 Gen1 and Gen2 with this PHY IP.

USB 3.1 UMC 28nm HPC In Production View all specifications

Overview

It supports both USB 3.1 Gen1 and Gen2 with this PHY IP. By offering a complete on-chip physical transceiver solution with built-in jitter injection, an integrated self-test module, and protection against Electro Static Discharge (ESD). This USB 3.1 Gen2 PHY IP can be used as a host or device and implements a USB 3.1 Gen2 transceiver. PHY IP supports Gen1 5Gbps data rate as well as USB3.1 Gen2 high speed data rates up to 10Gbps with integrated mixed signal circuit.

Key features

  • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
  • Supports 5.0Gbps and 10Gbps serial data transmission rate
  • Supports 16-bit or 32-bit parallel interface
  • Data and clock recovery from serial stream
  • Support 8b/10b encoder/decoder (Gen1), 128/132 encoder/ decoder (Gen2) and error indication
  • Tunable receiver detection to detect worse case cables
  • Low Frequency Periodic Signaling (LFPS) transmission and reception
  • Support SSCG function to reduce EMI effects with tunable down-spread amplitude
  • Selectable TX margining, TX de-emphasis and signal swing values
  • Built-in-self-test with internal Loopback test option
  • Programmable analog circuit parameter adjustment and internal test control
  • Compliant with USB3.1 Gen2 base specification
  • Silicon Proven in UMC 28HPC

Block Diagram

USB 3.1 Gen1/Gen2 PHY IP in 28HPC block diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behavior model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
USB 3.1 Gen1/Gen2 PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.1

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC?

USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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