USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC

The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption. The High-Speed USB 2.0 Transceiver is implemented by the USB2.0 IP and can be utilized with hosts, devices, or OTG function controllers. The USB2.0 PHY IP, which supports Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates, is the specification that comes after UTMI+level 3.High-speed data transfer @ 480Mbps can be achieved by combining several mixed-signal circuits. Additionally supported by the USB2.0 PHY IP are the enhanced USB Battery Charging standards, which are designed for use in consumer electronics and mobile devices. Numerous factories and nodes, including "TSMC 28HPC+, TSMC 40LP, TSMC 40LL, UMC 28HPC, UMC 40LP, UMC 55SP, UMC 55EF, SMIC 14SF+, SMIC 40LL, SMIC 55LL," implement the USB 2.0 PHY IP standard. Performance and data throughput were unaffected by the tiny chip size and low power consumption of the USB2.0 PHY IP ransceiver. The USB2.0 PHY IP offers a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit in order to fully enable host and device functionality.