Vendor: SmartDV Category: Single-Protocol PHY

LVDS Synthesizable Transactor

LVDS Synthesizable Transactor provides a smart way to verify the LVDS component of a SOC or a ASIC in Emulator or FPGA platform.

Overview

LVDS Synthesizable Transactor provides a smart way to verify the LVDS component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LVDS Synthesizable Transactor is fully compliant with standard LVDS Specification and provides the following features.

Key features

  • Follows LVDS Atmel-42415-WIRELESS-AT86RF215_Datasheet specification
  • Supports BBIC and RFIC Mode
  • Supports half duplex data transfer
  • Supports both data path transaction and SPI control interface transactions
  • Supports following IQ data path transaction
    • Supports TXD, RXD09 and RXD24
    • Supports 2bit I SYNC and Q SYNC data
    • Supports 14bit I data and Q data
    • Supports error injection
  • Supports following SPI control interface transaction
    • Supports 2bit command plus 14bit address and 8bit data control field format
    • Supports plane power consumption to negligible levels
    • Supports Master and Slave Mode
    • Supports baud rate selection
    • Supports single and burst transfer mode
  • Supports various kinds of errors as follows
    • I SYNC error
    • Q SYNC error
    • Invalid zero word error
    • Illegal write data error
    • Read only address error

Block Diagram

LVDS Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the LVDS testcases
  • Examples showing how to connect and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
LVDS Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Single-Protocol PHY IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Synthesizable Transactor?

LVDS Synthesizable Transactor is a Single-Protocol PHY IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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