Vendor: T2M GmbH Category: Single-Protocol PHY

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC

The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.

UMC 28nm HPC In Production View all specifications

Overview

The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption. It is capable of functioning in 10BASE-T, 100BASE-TX, and 1000BASE-T. This GPHY links the GMII-based Media Access Control Layer (MAC) (Giga Media Independent Interface). This GPHY uses either RGMII or GMII to connect to the Media Access Control Layer (MAC). It could support UTP5/UTP3 cable for 10BASE-Te Ethernet or Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet and 1000BASE-T Giga Ethernet. It includes all of the physical layer functionality of 100BASE-TX described by IEEE802.3u and 1000BASE-T defined by IEEE802.3ab, including the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), and Twisted Pair Physical Medium Dependent Sub-layer (TP-PMD, 100BASE-TX only).

Key features

  • Fully compliant with the IEEE 802.3 / 802.3u/802.3ab10BASE-Te, 100BASE-TX ,1000BASE-T
  • Interface available to Compliant with TP-PMD standard:ANSI X3.263-1995, Compliant with FDDIPMD standard: ISO/IEC 9314-3: 1990 and ANSIX3.166-1990
  • Support GMII / RGMII interface to the MAC controller.?Serial management interface compliant with IEEE802.3u (MDIO)
  • Support Full-Duplex or Half-Duplex Operation,1000BASE Full-Duplex only
  • Support Auto-Negotiation Next Page /Parallel Detection function compliant with IEEE 802.3u/ab, and Manual configuration is also supported.
  • Automatic Polarity Correction
  • Support auto MDI/MDIX crossover function for10BASE-Te / 100BASE-TX
  • Embedded baseline wander correction (BLW) Circuit
  • High Performance Digital Clock recovery algorithm
  • High performance Digital Equalizer for ISI mitigation
  • High performance Echo / NEXT canceller
  • Support Wake-On-Lan (WOL) with magic packet
  • Support efficient energy Ethernet (EEE), Compliant withIEEE802.3az-2010
  • Support automatic polarity swap
  • LED Driver for Link, Activity, Duplex, Collision, and Speed Status
  • Low Power design, with support 803.2az standard-2010(EEE)
  • Cable diagnostic Test (open/short/cable length)
  • Working Voltage 3.3/1.8/0.9
  • Crystal offset +/-300ppm
  • Silicon Proven in UMC 28nm HPC

Block Diagram

GbE (10/100/1000 Base-T) PHY IP in 28HPC block diagram

What’s Included?

  • Detailed Datasheet
  • Verilog behavior model (A) for simulation
  • Liberty (db / .lib) for synthesis, STA, and equivalence checking
  • CTL / CTLDB for DFT
  • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
  • LEF for APR
  • CDL for LVS connection
  • TSDB for MBIST (optional, U28 only)

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
GbE (10/100/1000 Base-T) PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC?

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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