Overview
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, devices, or OTG function controllers, the USB2.0 IP implements a High-Speed USB 2.0 transceiver. The USB2.0 PHY IP is compatible with Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates and complies with the UTMI+ level 3 specification. It integrates mixed-signal circuits to support High-Speed data rate at 480Mbps. The USB2.0 PHY IP also supports the additional USB Battery Charging requirements, which are aimed at mobile and consumer product applications. The USB2.0 PHY IP transceiver is designed to have a small chip size and low power consumption without compromising performance or data throughput. To enable complete support for host and device functionality, the USB2.0 PHY IP includes a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit.
Learn more about Single-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.
In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.
Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.
Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?
Enter the Inner Sanctum of RapidIO: Part 1
