Vendor: Faststream Technologies Category: Single-Protocol PHY

PCIe 3.0 PHY IP

We propound best in class fully customizable PCIe 3.0 PHY, targeted for both enterprise and client application, the complaint to …

PCIe Gen3 View all specifications

Overview

We propound best in class fully customizable PCIe 3.0 PHY, targeted for both enterprise and client application, the complaint to PCIe 3.0 specification. The PHY IP is designed to carry a broad range of applications and can supply maximum throughput through its eight lanes configuration. The PHY supports PCIE3.0(8Gb/s/5Gb/s/2.5Gb/s) physical layer specifications.The PHY module comprises a top-level wrapper combining both the Physical Media Attachment (PMA) layer and the Physical Coding Sub-Block (PCS) layer.
The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Key features

  • Physical coding sublayer (PCS) block with PIPE interface
  • PCIe 3.0 PHY with backward compatibility
  • Spread-spectrum clocking (SRIS)
  • Supports L0-L2 power states and L1.1 and L1.2 substates
  • Allows integration of high-speed components into a single functional block as seen by the endpoint device designer.
  • Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
  • Multi-channel PHY macro with a single clock and control core for higher density
  • Supports both internal and external reference clock inputs
  • Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
  • PIPE bifurcation as well as PHY macro aggregation for x8 and x16 PHY configurations
  • Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
  • Data and clock recovery from a serial stream on the PCI Express bus
  • 8b/10b encode/decode and error indication
  • Automated Test Equipment (ATE) test vectors for complete at-speed production testing

Benefits

  • Small size
  • Low power
  • Supports both internal and external reference clock inputs
  • High ATE coverage for complete at-speed production testing
  • Simple integration
  • Multi-channel PHY macro with a single clock and control core for higher density
  • Flexible customization

What’s Included?

  • Datasheet, Characterization Report
  • Comprehensive documentation and Support
  • GDSII ported to required process node
  • Physical Design scripts

Specifications

Identity

Part Number
FST-PCIE3-PHY
Vendor
Faststream Technologies
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen3

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is PCIe 3.0 PHY IP?

PCIe 3.0 PHY IP is a Single-Protocol PHY IP core from Faststream Technologies listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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