Vendor: V-Trans Microelectronics Category: Single-Protocol PHY

Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…

Contact Provider Request Datasheet

Overview

This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMOS data plus 10 control signals (VSYNC, HSYNC, DE, and 7 user-defined signals).

At a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gbps, providing a total maximum bandwidth of 11.9Gb/s (1.487Gbytes per second).

This IP can drive two (2) independent displays with resolution up to UXGA/Full HD (dual asynchronous input /output).

Key features

  • 1P7M/1P8M/1P9M/1P10M layout structure based on 65nm Logic 1P10M Salicide 1.2V/2.5V process.
  • 1.2V/2.5V ±10% supply voltage, -40/+125°C
  • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
  • Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
  • Dual independent single link mode (can drive 2 separate displays with different resolution)
  • Input clock detector (self reset when missing clock)
  • Spread-spectrum input clock support (can be used in SS systems)
  • Output Swing Control (2.5mA to 7mA programmable), PVT compensated
  • Input clock detector (self reset when missing clock)
  • Low leakage power-down mode <10uA
  • Core cell area : [contact us]
  • Power consumption [contact us]
  • Built-in power pads with ESD protection.
  • Equivalent part : Thine’s THC63LVD1025

Benefits

  • support full HDTV @120hz (3DTV)
  • Lowest bounding pad count
  • Low cost IP
  • reliability
  • highly adjustable
  • customization for your own design

What’s Included?

  • Design kit includes :
    • LEF view and abstract gdsII
    • Verilog HDL behavioral model
    • Liberty (.lib) timing constraints for typical, worse and best corner case
    • Full Datasheet /Application Note with integration guidelines document
    • Silicon characterization report when available
  • Tapeout kit includes the design kit plus plysical view:
    • gdsII
    • LVS netlist and report
    • DRC/ERC/ESD/ANT report

Specifications

Identity

Part Number
VT65LVD1025
Vendor
V-Trans Microelectronics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact V-Trans Microelectronics

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression?

Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression is a Single-Protocol PHY IP core from V-Trans Microelectronics listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP