Vendor: T2M GmbH Category: Single-Protocol PHY

SD4.1 UHS- II PHY IP

SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consum…

Samsung 14nm In Production View all specifications

Overview

SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consumption. This PHY IP is versatile, suitable for use on both the device and host sides, including SDIO. Therefore, it can be integrated into SOCs for a wide range of applications such as SD cards, digital cameras, digital videos, digital TVs, media players, and personal computers.

Key features

  • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
  • 16bit interface to Link layer
  • Supports both Full Duplex mode and Half Duplex mode
  • Wide range channel speed up to 1.56Gbps
  • Power saving mode
  • Configurable analog characteristics
  • Driver swing voltage
  • Testability:Built-in scan test
  • Area: <1mm2
  • Process: - SAMSUNG14nm 1.8V/0.8V

Block Diagram

What’s Included?

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/DRC results
  • Verilog RTL or netlist of digital part

Silicon Options

Foundry Node Process Maturity
Samsung 14nm 14nm 140 nm In Production

Specifications

Identity

Part Number
SD4.1 UHS- II PHY IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

Learn more about Single-Protocol PHY IP core

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In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is SD4.1 UHS- II PHY IP?

SD4.1 UHS- II PHY IP is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for samsung In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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