CDM Dependence on Device Capacitance
This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.
Vendor:
Certus Semiconductor
Category:
Single-Protocol PHY
LVDS RX & TX IOs in multiple foundry technology
Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies.
Overview
Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies. The Certus LVDS solutions are ANSI/TIA/EIA-644-A compliant and are capable of data rates of up to 1.5Mbps. Unique to the Certus LVDS solution is that it is self-biased with no external reference blocks required. Our LVDS cell configurations also allow for flexible supply pad arrangements and dense IO placement without compromising signal integrity.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we address standard ESD such as HBM and CDM, but we can also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, SD, I2C, SMBUS, DDC, Analog/RF, HV and other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features to suit your needs.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we address standard ESD such as HBM and CDM, but we can also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, SD, I2C, SMBUS, DDC, Analog/RF, HV and other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features to suit your needs.
Key features
- LVDS TX
- Output enable
- Internally generated common mode reference (no external pin required)
- Power-on sequence independence
- ESD protection of 2KV HBM, 500V CDM
- LVDS RX
- Input enable
- Built-in 100? RX termination resistor
- Fault-safe mode for shorted or open RX pins
- Power-on sequence independence
- ESD protection of 2KV HBM, 500V CDM
Block Diagram
Certus LVDS Solutions block diagram
Benefits
- Self-biased - no external reference required
- Fail-safe
- Flexible pad arrangements
- Power sequence independence
- Proven HBM & CDM ESD protection
Applications
- LVDS
What’s Included?
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | GP | Silicon Proven |
Specifications
Identity
Part Number
Certus LVDS Solutions
Vendor
Certus Semiconductor
Type
Silicon IP
Provider
HQ:
United States
Learn more about Single-Protocol PHY IP core
A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library
As semiconductor designs continue to diversify, many successful products are not chasing the most advanced process nodes. Instead, they prioritize power efficiency, reliability, and long-term availability.
Field Induced CDM Explained
Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.
One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.
Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
As a member of the TSMC IP Alliance, Certus delivers production-proven IP that ensures seamless integration with TSMC process nodes, ranging from 180nm to 12nm.
Unlocking High-Speed Connectivity with Certus Semiconductor’s LVDS Transceiver on GlobalFoundries 12LP/LP+
In today’s data-driven world, high-speed, low-power communication is essential. Certus Semiconductor’s LVDS Transceiver delivers exactly that—optimized for GlobalFoundries’ 12nm CMOS process, it provides reliable, high-performance Low-Voltage Differential Signaling (LVDS) for next-generation designs.
Frequently asked questions about Single-Protocol PHY IP
What is LVDS RX & TX IOs in multiple foundry technology?
LVDS RX & TX IOs in multiple foundry technology is a Single-Protocol PHY IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.