Vendor: T2M GmbH Category: Single-Protocol PHY

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC

Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver f…

UMC 28nm HPC In Production View all specifications

Overview

Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver for 10BASE-Te, 100BASE-TX, operation. Through the Giga Media Independent Interface (GMII), the EPHY connects to the Media Access Control Layer (MAC), and on the media side, it provides a direct interface either to Un-shielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet or UTP5/UTP3 cable for 10BASE-Te Ethernet. The Ethernet PHY employ a low power and high-performance CMOS process. It contains the entire physical layer function of 100BASE-TX defined by IEEE802.3u, including the Physical Coding Sub- ayer (PCS), Physical Medium Attachment Layer(PMA), Twisted Pair Physical medium Dependent Sub-layer (TP-PMD, 100BASE-TX only). The EPHY also provide a robust auto-negotiation function, utilizing automatic media speed/duplex and protocol selection match. EPHY also support Auto MDI/MDIX function to simplify the network installation.

Key features

  • Fully compliant with the IEEE 802.3 / 802.3u 10BASE-Te, 100BASE-TX
  • Interface available to Compliant with TP-PMD standard: ANSI X3.263-1995
  • Compliant with FDDI-PMD standard: ISO/IEC 9314-3: 1990 and ANSI X3.166-1990
  • Support GMII interface to the MAC controller.
  • Serial management interface compliant with IEEE 802.3u (MDIO)
  • Support Full-Duplex or Half-Duplex Operation
  • Support Auto-Negotiation Next Page /Parallel Detection function
  • Compliant with IEEE 802.3u, and Manual configuration is also supported.
  • Automatic Polarity Correction
  • Support auto MDI/MDIX crossover function for 10BASE-Te / 100BASE-TX
  • High performance baseline wander correction (BLW) Circuit
  • High Performance Digital Clock recovery algorithm
  • High performance Digital Equalizer for ISI mitigation
  • LED Driver for Link, Activity, Duplex, Collision, and Speed Status
  • Low Power design, with support 803.2az standard-2010 (EEE)
  • Support MAX 300ppm sampling offset
  • Silicon Proven in UMC 28nm HPC+

Block Diagram

Applications

  • Detailed Datasheet
  • Verilog behaviour model (A) for simulation
  • Liberty (db./.lib) for synthesis, STA, and equivalence checking
  • CTL / CTLDB for DFT
  • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
  • LEF for APR
  • CDL for LVS connection

What’s Included?

  • Detailed Datasheet
  • Verilog behavior model (A) for simulation
  • Liberty (db / .lib) for synthesis, STA, and equivalence checking
  • CTL / CTLDB for DFT
  • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
  • LEF for APR
  • CDL for LVS connection

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
GbE (10/100 Base-T) PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

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Frequently asked questions about Single-Protocol PHY IP

What is GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC?

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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