Vendor: Key ASIC Category: Single-Protocol PHY

USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps

KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits.

Overview

KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits. The PHY can be configured for either an 8-bit or a 16-bit parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480bps transfer rate, while remaining backward compatible with USB1.1 legacy protocol at 12Mbps.

It includes the following blocks:
* Analog Driver and Receiver
* PLL generate the 480MHz clock
* Clock and Data Recovery
* NRZI encoder/decoder
* Serialize / De-serialize
* Control state machine
* Integrated pull up and self-calibrated termination resistors and switches

Key features

  • Complies with Universal Serial Bus Specification Rev. 2.0
  • Interface compliant with the UTMI specification (60MHz 8-bit interface or 30MHz 16-bit interface)
  • Supports 480Mbps High-Speed(HS) and 12Mbps Full-Speed(FS)
  • Serial data transmission rates
  • Built-In Self Test (BIST)
  • Integrated Self-Calibrated termination resistors (45 ohm) and built-in 1.5K ohm
  • Power supply: VDD33=3.3V ±10%, VP12=1.2V ±10%
  • Operating temperature: -40°C~ +125°C

Block Diagram

KA13UGUSB20ST001 block diagram

Benefits

  • Physical layer transceiver (PHY), 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
  • Supports 480bps transfer rate, while remaining backward compatible with USB1.1 legacy protocol at 12Mbps.

Applications

  • Digital Video camera
  • Scanner
  • Printer
  • External storage devices, e.g.Portable hard disk, Optical drive (CD-ROM, CD-RW, DVD)

What’s Included?

  • Data Sheet
  • Integration guide
  • LEF
  • Timing LIB
  • Verilog PHY behavioral model and BIST test-benches
  • EVB schematic and user guide

Specifications

Identity

Part Number
KA13UGUSB20ST001
Vendor
Key ASIC
Type
Silicon IP

Provider

Key ASIC
HQ: Malaysia

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Frequently asked questions about Single-Protocol PHY IP

What is USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps?

USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps is a Single-Protocol PHY IP core from Key ASIC listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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