Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detail…
- TSMC
- 28nm
- Silicon Proven
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detail…
112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networki…
224G Ethernet PHY for TSMC 3nm
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth…
The 224G SerDes PHY enables the emerging 1.6T and 800G networks for hyperscale data center and artificial intelligence (AI) infrastructures.
The 56G Long-Reach (LR) SerDes PHY provides exceptional performance with best-in-class power and area, making it ideal for machine learning (ML) and 5G infrastructure application
ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash c…
LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and…
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to mee…
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
PCIe 4.0 PHY in Samsung (14nm, 11nm, SF5A, SF2)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
PCIe 2.0 PHY in UMC (40nm, 28nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…
PCIe 2.0 PHY in TSMC (28nm, 16nm, 12nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…
PCIe 2.0 PHY in SMIC (40nm, 28nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…
PCIe 2.0 PHY in Fujitsu (40nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…
56G Ethernet PHY in TSMC (16nm, 12nm)
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…
12G Ethernet PHY in UMC (28nm)
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…
USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E)
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.
USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.