Vendor: T2M GmbH Category: Single-Protocol PHY

ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)

ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash c…

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TSMC 28nm HPC+ In Production View all specifications

Overview

ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY.

Key features

  • Support ONFi 4.0 IO Electrical Specification
  • Support Legacy up to 50MHz
  • Support NV-DDR2 with operating frequency up to 533Mbps
  • Support NV-DDR3 with operating frequency up to 800Mbps
  • Per DQ (per bit) delay line for controlling skew
  • SDLL is included for DQS/DQ phase tuning by DLY setting
  • On die De-coupling capacitor (>1nF per channel) for Power Integrity to save PKG capacitor
  • Operation temperature: -40 to 125 °C
  • Programmable output impedance
  • TSMC 28nm HPCP 1P7M5X1R (HVT/LVT/EHVT) process
  • Wire-bond

Block Diagram

ONFi 4.0 PHY IP block diagram

Benefits

  • Silicon Proven in TSMC 28HPC+
  • In Production in multiple Chipsets

Applications

  • SSD
  • NAND Flash Chips

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard Delay Format (SDF)
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 28nm HPC+ In Production

Specifications

Identity

Part Number
ONFi 4.0 PHY IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

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Frequently asked questions about Single-Protocol PHY IP

What is ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)?

ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+) is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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