LVDS / sub-LVDS / DPHY TX - TSMC 6FFC

The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams. A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link. The polarity of differential signals for each data lane can be controlled. The CL12661M10T2DM2FIP transmitter is an ideal means to solve EMI and cable size issues associated with high-speed CMOS interface.
* This IP is expandable to 4, 5, 8, 10 or more lanes.
* Porting is also possible for processes other than the target process.
* We can provide the original LINK controller (soft macro) that can be used with this PHY.

• Data Rate: Up to 1.0 Gbps for LVDS, subLVDS / 2.5Gbps for DPHY
• Clock polarity programmable
• Data polarity for each data lane is programmable
• Integrated Integer-N PLL
• 4 programable level of output differential voltage
• BIST function for loopback test
• Operational modes supported:
  •  to support LVDS dual link (5 data lanes + 1 clock lane) x 2 channel
  •  to support subLVDS link (5 data lanes + 1 clock lane) x 2 channel
  •  to support DPHY TX @ 2.5Gbps (4 data lanes + 1 clock lane)

• This IP has three operating modes and supports connection to a variety of displays.
• By developing an SOC equipped with this IP, customers can select the optimal interface from three interface types by changing the internal settings.
• This increases the flexibility of connected displays.
• In addition, LVDS mode allows amplitude adjustment when using long cables, increasing the flexibility of the connection environment.
• We can also supply link controllers that are compatible with this combo PHY.
• This IP can be implemented in a lane units and can be tailored to meet customer specifications.

• Display Application
  • Automotive
  • Navigation system
  • DSC(Digital Still Camera)

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• RX Verilog Model and Test Vector(Option)
• Combo Link Layer IP(CD12661IP) and FPGA Board(Option)