The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
- VESA DSC
- DK Ready
- Now
- VESA DSC 1.2b
Multimedia Interface IP cores provide the high-speed connectivity technologies required to transport video, audio, image, and display data across modern SoCs, ASICs, and electronic systems. These interfaces are essential for enabling seamless communication between processors, cameras, displays, sensors, and multimedia subsystems.
This category includes HDMI, DisplayPort, MIPI, V-By-One, and VESA DSC (Display Stream Compression) IP solutions. Available implementations may include controllers, PHYs, protocol stacks, bridge solutions, and complete subsystem IP supporting high-resolution displays, camera interfaces, video transport, display compression, and multimedia data exchange.
Compare multimedia interface IP cores by protocol standard, feature set, implementation model, and vendor offering to support your video, display, and media connectivity roadmap.
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The DSC Encoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX).
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-h…
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices.
The DisplayPort Multi Stream Transport (MST) Topology Management Software implements MST topology management for multiple monitor…
DisplayPort 1.4a / eDP 1.4b TX PHY and Controller IP
Comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards
DisplayPort 1.4a / eDP 1.4b RX PHY and Controller IP
Comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards
The Foresys MIPI CSI2 Tx Core provides a fast path to integrating Image Sensors into a wide variety of products based on Altera d…
The Foresys MIPI Core provides a fast path to integrating Image Sensors or other MIPI connected devices into a wide variety of pr…
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MIPI SPMI Controller or Target
The SPMI-CTRL core implements a featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus.
Two Input to One Output MIPI CSI-2 Camera Aggregator Bridge
Many new applications such as augmented reality, depth perception and gesture recognition require multiple image sensor interface…
SubLVDS to MIPI CSI-2 Image Sensor Bridge
Most off-the-shelf Application Processors use industry standard interfaces such as MIPI CSI-2.
RGB to MIPI DSI Display Interface Bridge
Most mobile displays use industry standard interfaces such as MIPI DSI for interface connectivity.
OpenLDI LVDS to MIPI DSI Display Interface Bridge
Most mobile displays use industry standard interfaces such as MIPI DSI for interface connectivity.
One Input to Two Output MIPI DSI Display Splitter Bridge
Many new applications such as virtual reality, augmented reality, and digital cameras require expansion of the number of display …